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is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 1 rev. c 1 11/12 /2014 128 mx8, 64 mx16 1 g b ddr 3 s dram november 201 4 features ? standard voltage: v dd and v ddq = 1. 5 v 0. 075 v ? low voltage (l): v dd and v ddq = 1.3 5 v + 0. 1 v, - 0.067v - backward compatible to 1.5v ? high speed data transfer rates with system frequency up to 1066 mhz ? 8 internal banks for concurrent operation ? 8 n - bit pre - fetch architecture ? programmable cas latency ? programmable additive latency: 0, cl - 1,cl - 2 ? programmable cas write latency (cwl) based on t ck ? programmable burst length: 4 and 8 ? programmable burst sequence: sequential or interleave ? bl switch on the fly ? auto self refresh (asr) ? self refresh temperature(srt) ? refresh interval: 7.8 us (8192 cycles/64 ms) tc = - 40c to 85c 3.9 us (8192 cycles/32 ms) tc = 85 c to 10 5 c ? partial array self refresh ? asynchronous reset pin ? tdqs (termination data strobe) supported (x8 only) ? ocd (off - chip driver impedance adjustment) ? dynamic odt (on - die termination ) ? driver s tre ngth : rzq/7, rzq/6 (rzq = 240 ? ) ? write leveling ? operating temperature: commercial ( t c = 0c to +95 c ) industrial ( t c = - 40c to +9 5c ) automotive , a1 ( t c = - 40c to +9 5c) automotive , a2 ( t c = - 40c to +10 5c) options ? configuration: 128mx8 64mx16 ? package: 96 - ball fbga (9mm x 13mm) for x16 78 - ball fbga (8mm x 10.5mm) for x 8 address table parameter 128 mx 8 64 mx16 row addressing a0 - a1 3 a0 - a1 2 column addressing a0 - a 9 a0 - a 9 bank addressing ba 0 - 2 ba 0 - 2 page size 1 kb 2kb auto precharge addressing a10 /ap a10 /ap bl switch on the fly a12 /bc# a12 /bc# speed bin speed option 15g 125j 107m 093n units jedec speed grade ddr3 - 1333g ddr3 - 1600j ddr3 - 1866m ddr3 - 2133 n cl - nrcd - nrp 8 - 8 - 8 10 - 10 - 10 13 - 13 - 1 3 14 - 14 - 14 tck trcd,trp(min) 12.0 12.5 13.91 13. 09 ns note: faster speed options may be backward compatible to slower speed options. refer to timing tables (8.3) copyright ? 2014 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specification and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orde rs for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness . products are not authorized f or use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 2 rev. c 1 11/12 /2014 1. ddr3 package b allout 1.1 ddr 3 sdram package ballout 78 - ball fbga C x 8 1 2 3 4 5 6 7 8 9 a vss vdd nc nu/tdqs# vss vdd b vss vssq dq0 dm/tdqs vssq vddq c vddq dq2 dqs dq1 dq3 vssq d vssq dq6 dqs# vdd vss vssq e vrefdq vddq dq4 dq7 dq5 vddq f nc 1 vss ras# ck vss nc g odt vdd cas# ck# vdd cke h nc cs# we# a10/ap zq nc j vss ba0 ba2 nc( a15 ) vrefca vss k vdd a3 a0 a12/bc# ba1 vdd l vss a5 a2 a1 a4 vss m vdd a7 a9 a11 a6 vdd n vss reset# a13 nc( a14 ) a8 vss note: nc balls have no internal connection. nc ( a 14 ) and nc( a 15 ) are one of nc pins and reserved for higher densities . 1.2 ddr 3 sdram package ballout 96 - ball fbga C x16 1 2 3 4 5 6 7 8 9 a vddq dqu5 dqu7 dqu4 vddq vss b vssq vdd vss dqsu# dqu6 vssq c vddq dqu3 dqu1 dqsu dqu2 vddq d vssq vddq dmu dqu0 vssq vdd e vss vssq dql0 dml vssq vddq f vddq dql2 dqsl dql1 dql3 vssq g vssq dql6 dqsl# vdd vss vssq h vrefdq vddq dql4 dql7 dql5 vddq j nc vss ras# ck vss nc k odt vdd cas# ck# vdd cke l nc cs# we# a10/ap zq nc m vss ba0 ba2 nc( a15 ) vrefca vss n vdd a3 a0 a12/bc# ba1 vdd p vss a5 a2 a1 a4 vss r vdd a7 a9 a11 a6 vdd t vss reset# nc( a13 ) nc( a14 ) a8 vss note: nc balls have no internal connection. nc ( a 13 ) , nc ( a 14 ) and nc( a 15 ) are one of nc pins and reserved for higher densities .
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 3 rev. c 1 11/12 /2014 1. 3 pinout description - jedec standard symbol type function ck, ck# input clock: ck and ck# are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck#. cke input clock enable: cke high activates, and cke low deactivates, internal clock sig nals and device input buffers and output drivers. taking cke low provides precharge power - down and self - refresh operation (all banks idle), or active power - down (row active in any bank). cke is asynchronous for self - refresh exit. after vrefca and vrefdq ha ve become stable during the power on and initialization sequence, they must be maintained during all operations (including self - refresh). cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck#, odt and cke, are dis abled during power - down. input buffers, excluding cke, are disabled during self - refresh. cs# input chip select: all commands are masked when cs# is registered high. cs# provides for external rank selection on systems with multiple ranks. cs# is considered part of the command code. odt input on die termination: odt (registered high) enables termination resistance internal to the ddr3 sdram. when enabled, odt is only applied to each dq, dqsu, dqsu#, dqsl, dqsl#, dmu, and dml signal. the odt pin will be ignored if mr1 and mr2 are programmed to disable rtt. ras#. cas#. we# input command inputs: ras#, cas# and we# (along with cs#) define the command being entered. dm, (dmu), (dml) input input data mask: dm is an input mask signal for write data. input dat a is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. for x8 device, the function of dm or tdqs/tdqs# is enabled by mode register a11 setting in mr1. ba0 - ba2 input bank address inputs: ba0 - ba2 define to which bank an active, read, write, or precharge command is being applied. bank address also determines which mode register is to be accessed during a mrs cycle. a0 - a13 input address inputs: provide the row address for active commands and the column address for read/ write commands to select one location out of the memory array in the respective bank. (a10/ap and a12/bc# have additional functions; see below). the address inputs also provide the op - code during mode register set commands. a10 / ap input auto - precharge: a10 is sampled during read/write commands to determine whether autoprecharge should be performed to the accessed bank after the read/write operation. (high: autoprecharge; low: no autoprecharge). a10 is sampled dur ing a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by bank addresses. a12 / bc# input burst chop: a12 / bc# is sampled during read and write commands to determine if burst chop (on - the - fly) will be performed. (high, no burst chop; low: burst chopped). see command truth table for details. reset# input active low asynchronous reset: reset is active when reset# is low, and inactive when reset# is high. reset# must be high during normal operation. reset# is a cmos rail - to - rail signal with dc high and low at 80% and 20% of vdd, i.e., 1.20v for dc high and 0.30v for dc low. dq (dql, dqu) input / output data input/ output: bi - directional da ta bus. dqs, dqs#, dqsu, dqsu#, dqsl, dqsl# input / output data strobe: output with read data, input with write data. edge - aligned with read data, centered in write data. for the x16, dqsl corresponds to the data on dql0 - dql7; dqsu corresponds to the data on dqu0 - dqu7. the data strobes dqs, dqsl, and dqsu are paired with differential signals dqs#, dqsl#, and dqsu#, respectively, to provide differential pair signaling to the system during reads and writes. ddr3 sdram supports differential data strobe only a nd does not support single - ended. tdqs, tdqs# output termination data strobe: tdqs/tdqs# is applicable for x8 drams only. when enabled via mode register a11 = 1 in mr1, the dram will enable the same termination resistance function on tdqs/tdqs# that is applied to dqs/dqs#. when disabled via mode register a11 = 0 in mr1, dm/tdqs will provide the data mask function and tdqs# is not used. x16 drams must disable the tdqs function via mode register a11 = 0 in mr1. nc no connect: no internal electrical connection is present. vddq supply dq power supply: 1.5 v +/ - 0.075 v for standard voltage or 1.35v +0.1v, - 0.067v for low voltage vssq supply dq ground
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 4 rev. c 1 11/12 /2014 vdd supply power supply: 1.5 v +/ - 0.075 v for standard voltage or 1.35v +0.1v, - 0.067v for low voltage vss supply ground vrefdq supply reference voltage for dq vrefca supply reference voltage for ca zq supply reference pin for zq note: input only pins (ba0 - ba2, a0 - a13, ras#, cas#, we#, cs#, cke, odt, and reset#) do not supply termination.
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 5 rev. c 1 11/12 /2014 2. function descript ion 2.1 simplified state diagram abbreviation function abbreviation function abbreviation function act active read rd, rds4, rds8 pde enter power - down pre precharge read a rda, rdas4, rdas8 pdx exit power - down prea precharge all write wr, wrs4, wrs8 sre self - refresh entry mrs mode register set write a wra, wras4, wras8 srx self - refresh exit ref refresh reset start reset procedure mpr multi - purpose register zqcl zq calibration long zqcs zq calibration short p ower on p ower applied reset from any state reset procedure initialization zqcl zq calibration zqcl zqcs idle mrs,mpr, write leveling self refresh sre srx ref refreshing precharge power down pdx pde act activating bank active active power down pde pdx reading writing writing reading precharging automatic sequence command sequence write write write a write write a write a pre,prea read read a read read a pre,prea pre,prea read a read
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 6 rev. c 1 11/12 /2014 2.2 reset and initialization procedure 2.2.1 power - up initialization sequence the following sequence is required for power up and initialization. 1. apply power (reset# is recommended to be maintained below 0.2 x vdd; all other inputs may be undefined). reset# needs to be maintained for minimum 200 us with stable power. cke is pulled low anytime before reset# being de - asserted (min. time 10 ns). the power voltage ramp time between 300m v to vdd ( min ) must be no greater than 200 m s; and during the ramp, vdd > vddq and (vdd - vddq) < 0.3 volts. ? vdd and vddq are driven from a single power converter output, and ? the voltage levels on all pins other than vdd, vddq, vss, vssq must be less than or equal to vddq and vdd on one side and mu st be larger than or equal to vssq and vss on the other side. in addition, vtt is limited to 0.95 v max once power ramp is finished, and ? vref tracks vddq/2. or ? apply vdd without any slope reversal before or at the same time as vddq. ? apply vddq without any slope reversal before or at the same time as vtt & vref. ? the voltage levels on all pins other than vdd, vddq, vss, vssq must be less than or equal to vddq and vdd on one side and must be larger than or equal to vssq and vss on the other side. 2. after reset# is de - asserted, wait for another 500 us until cke becomes active. during this time, the dram will start internal state initialization; this will be done independently of external clocks. 3. clocks (ck, ck#) need to be started and stabilized for at least 10 ns or 5 tck (which is larger) before cke goes active. since cke is a synchronous signal, the corresponding set up time to clock (tis) must be met. also, a nop or deselect command must be registered (with tis set up time to clock) before cke goes active. on ce the cke is registered high after reset, cke needs to be continuously registered high until the initialization sequence is finished, including expiration of tdllk and tzqinit. 4. the ddr3 sdram keeps its on - die termination in high - impedance state as lo ng as reset# is asserted. further, the sdram keeps its on - die termination in high impedance state after reset# deassertion until cke is registered high. the odt input signal may be in undefined state until tis before cke is registered high. when cke is reg istered high, the odt input signal may be statically held at either low or high. if rtt_nom is to be enabled in mr1, the odt input signal must be statically held low. in all cases, the odt input signal remains static until the power up initialization seque nce is finished, including the expiration of tdllk and tzqinit. 5. after cke is being registered high, wait minimum of reset cke exit time, txpr, before issuing the first mrs command to load mode register. (txpr=max (txs ; 5 x tck) 6. issue mrs command to load mr2 with all application settings. (to issue mrs command for mr2, provide low to ba0 and ba2, high to ba1.) 7. issue mrs command to load mr3 with all application settings. (to issue mrs command for mr3, provide low to ba2, high to ba0 and ba1.) 8. issue mrs command to load mr1 with all application settings and dll enabled. (to issue "dll enable" command, provide "low" to a0, "high" to ba0 and "low" to ba1 C ba2).
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 7 rev. c 1 11/12 /2014 9. issue mrs command to load mr0 with all application settings and dll reset. (to issue dll reset c ommand, provide "high" to a8 and "low" to ba0 - 2). 10. issue zqcl command to starting zq calibration. 11. wait for both tdllk and tzqinit completed. 12. the ddr3 sdram is now ready for normal operation. figure2.1.1 reset and initialization sequence at power - on ramping ta ck,ck# vdd,vddq reset# cke cmmand ba odt rtt tb t=200s tmin=10ns t =5 00s tcksrx tis tis tis ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) tc td ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) txpr tmrd tmrd tmrd tmod tzqinit t dllk tis valid valid valid valid mrd mrd mrd mrd zqcl 1) mr 2 mr 3 mr 1 mr 0 ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) te tf tg th ti tj tk note1. from time point td until tk nop or des commands must be applied between mrs and zqcl commands. time break dont care static low in case rtt_nom is enabled at time tg, otherwise static high or low 1)
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 8 rev. c 1 11/12 /2014 2.2.2 reset initialization with stable power the following sequence is required for reset at no power interruption initialization. 1. asserted reset below 0.2 * vdd anytime when reset is needed (all other inputs may be undefined). reset needs to be maintained for minimum 100 ns. cke is pulled low before reset being de - asserted (min. time 10 ns). 2. follow power - up initialization sequence steps 2 to 11. 3. the reset sequence is now completed; ddr3 sdram is ready for normal op eration. figure2.1.2 reset procedure at power stable condition 2.3 register definition 2.3.1 programming the mode registers for application flexibility, various functions, features, and modes are programmable in four mode registers, provided by the ddr3 sdram, as user defined variables and they must be programmed via a mode register set (mrs) command. as the default values of the mode registers (mr#) are not defined, contents of mode registers must be fully initialized and/or re - initialized, i.e. wri tten, after power up and/or reset for proper operation. also the contents of the mode registers can be altered by re - executing the mrs command during normal operation. when programming the mode registers, even if the user chooses to modify only a sub - set o f the mrs fields, all address fields within the accessed mode register must be redefined when the mrs command is issued. mrs command and dll reset do not affect array contents, which means these commands can be executed any time after power - up without affe cting the array contents the mode register set command cycle time, tmrd is required to complete the write operation to the mode register and is the minimum time required between two mrs commands shown as below. ta ck,ck# vdd,vddq reset# cke cmmand ba odt rtt tb t=100ns tmin=10ns t =5 00s tcksrx tis tis tis ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) tc td ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) txpr tmrd tmrd tmrd tmod tzqinit t dllk tis valid valid valid valid mrd mrd mrd mrd zqcl 1) mr 2 mr 3 mr 1 mr 0 ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) te tf tg th ti tj tk note1. from time point td until tk nop or des commands must be applied between mrs and zqcl commands. time break dont care static low in case rtt_nom is enabled at time tg, otherwise static high or low 1)
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 9 rev. c 1 11/12 /2014 figure2.3.1a tmrd timing the mrs command to non - mrs command delay, tmod, is require for the dram to update the features except dll reset, and is the minimum time required from an mrs command to a non - mrs command excluding nop and des shown as the following figure. figure 2.3.1b tmod timing the mode register contents can be changed using the same command and timing requirements during nor mal operation as long as the dram is in idle state, i.e., all banks are in the precharged state with trp satisfied, all data bursts are completed and cke is high prior to writing into the mode register. if the rtt_nom feature is enabled in the mode register prior and/or after an mrs command, the odt signal must continuously be registered low ensuring rtt is in an off state prior to the mrs command. the odt signal maybe registered high after tmod has expired. if the rtt_nom fea ture is disabled in the mode register prior and after an mrs command, the odt signal can be registered either low or high before, during and after the mrs command. the mode registers are divided into various fields depending on the functionality and/or mod es. ck# ck command address cke settings odt odt rtt_nom enabled prior and/or after mrs command rtt_nom disabled prior and after mrs command odtloff + 1 old settings ( ( ) ) time break dont care valid valid valid valid valid valid valid valid valid valid valid valid mrs valid valid nop/ dec valid valid valid valid mrs valid valid valid valid valid valid valid valid valid valid valid valid nop/ dec nop/ dec nop/ dec tmrd tmrd new settings ck# ck command address cke settings odt odt rtt_nom enabled prior and/or after mrs command rtt_nom disabled prior and after mrs command odtloff + 1 old settings ( ( ) ) time break dont care valid valid valid valid valid valid valid valid valid valid valid valid mrs valid valid nop/ dec valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid nop/ dec nop/ dec nop/ dec tmod new settings nop/ dec
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 10 rev. c 1 11/12 /2014 2.3.2 mode register mr0 the mode register mr0 stores the data for controlling various operat ing modes of ddr3 sdram. it con trols burst length, read burst type, cas latency, test mode, dll reset, wr and dll control for precharge power - dow n, which include vendor specific options to make d dr3 sdram useful for various ap plications. the mode register is written by asserting low on cs#, ras#, cas#, we#, ba0, ba1, and ba2, while controlling the states of address pins according to the following f igure. 1. a13 must be programmed to 0 during mrs. 2. wr (write recovery for autoprecharge)min in clock cycles is calculated by dividing twr(in ns) by tck(in ns) and rounding up t o the next integer: wrmin[cycles] = roundup(twr[ns] / tck[ns]). the wr value in the mode register must be programmed to be equal or larger than wrmin. the programmed wr value is used with trp to determine tdal. 3. the table only shows the encodings for a given cas latency. for actual supported cas latency, please refer to speedbin tables for each frequency 4. the table only shows the encodings for write recovery. for actual write recovery timing, please refer to ac timing table. figure 2.3.2 mr0 definition 2 . 3 .2.1 burst length, type and order accesses within a given burst may be programmed to sequential or interleaved order. the burst type is selected via bit a3 as shown in figure 2.3.2 . the ordering of accesses within a burst is determined by the burst length, burst type, and the starting co lumn address as shown in table below . the burst length is defined by bits a0 - a1. burst length options include ba2 ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 0 0 0* 1 ppd wr dll tm cas latency rbt cl bl mode register 0 a8 dll reset a7 mode a3 read burst type a1 a0 bl 0 no 0 nomal 0 nibble sequential 0 0 8 (fixed) 1 yes 1 test 1 interleave 0 1 bc4 or 8 (on the fly) 1 0 bc4 (fixed) a12 dll control for write recovery for autoprecharge 1 1 reserved precharge pd a11 a10 a9 wr(cycles) 0 slow exit (dll off) 0 0 0 16 *2 a6 a5 a4 a2 cas latency 1 fast exit (dll on) 0 0 1 5 *2 0 0 0 0 reserved 0 1 0 6 *2 0 0 1 0 5 ba1 ba0 mr select 0 1 1 7 *2 0 1 0 0 6 0 0 mr0 1 0 0 8 *2 0 1 1 0 7 0 1 mr1 1 0 1 10 *2 1 0 0 0 8 1 0 mr2 1 1 0 12 *2 1 0 1 0 9 1 1 mr3 1 1 1 14 *2 1 1 0 0 10 1 1 1 0 11 0 0 0 1 12 0 0 1 1 13 0 1 0 1 14 0 1 1 1 15 1 0 0 1 16 1 0 1 1 reserved 1 1 0 1 reserved 1 1 1 1 reserved
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 11 rev. c 1 11/12 /2014 fixed bc4, fixed bl8, and on the fly which allows bc4 or bl8 to be selected coincident with the registration of a read or write command via a12/ bc#. burst length read/ write starting column address (a2,a1,a0) burst type = sequential (decimal) a3 = 0 burst type = interleaved (decimal) a3 = 1 notes 4 chop read 0 0,1,2,3,t,t,t,t 0,1,2,3,t,t,t,t 1, 2, 3 1 1,2,3,0,t,t,t,t 1,0,3,2,t,t,t,t 1, 2, 3 10 2,3,0,1,t,t,t,t 2,3,0,1,t,t,t,t 1, 2, 3 11 3,0,1,2,t,t,t,t 3,2,1,0,t,t,t,t 1, 2, 3 100 4,5,6,7,t,t,t,t 4,5,6,7,t,t,t,t 1, 2, 3 101 5,6,7,4,t,t,t,t 5,4,7,6,t,t,t,t 1, 2, 3 110 6,7,4,5,t,t,t,t 6,7,4,5,t,t,t,t 1, 2, 3 111 7,4,5,6,t,t,t,t 7,6,5,4,t,t,t,t 1, 2, 3 write 0,v,v 0,1,2,3,x,x,x,x 0,1,2,3,x,x,x,x 1, 2, 4, 5 1,v,v 4,5,6,7,x,x,x,x 4,5,6,7,x,x,x,x 1, 2, 4, 5 8 read 0 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 2 1 1,2,3,0,5,6,7,4 1,0,3,2,5,4,7,6 2 10 2,3,0,1,6,7,4,5 2,3,0,1,6,7,4,5 2 11 3,0,1,2,7,4,5,6 3,2,1,0,7,6,5,4 2 100 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 2 101 5,6,7,4,1,2,3,0 5,4,7,6,1,0,3,2 2 110 6,7,4,5,2,3,0,1 6,7,4,5,2,3,0,1 2 111 7,4,5,6,3,0,1,2 7,6,5,4,3,2,1,0 2 write v,v,v 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 2, 4 notes: 1. in case of burst length being fixed to 4 by mr0 setting, the internal write operation starts two clock cycles earlier than for the bl8 mode. this means that the starting point for twr and twtr will be pulled in by two clocks. in case of burst length being selected on - the - fly via a12/bc#, the internal write operation starts at the same point in time like a burst of 8 write operation. this means that during on - the - fly control, the starting point for twr and twtr will not be pulled in by two clocks. 2. 0.. .7 bit number is value of ca[2:0] that causes this bit to be the first read during a burst. 3. t: output driver for data and strobes are in high impedance. 4. v: a valid logic level (0 or 1), but respective buffer input ignores level on input pins. 5. x: dont care . 2 . 3 .2. 2 cas latency the cas latency is defined by mr0 (bits a9 - a11) as shown in figure 2.3.2 . cas latency is the delay, in clock cycles, between the internal read command and the availability of the first bit of output data. ddr3 sdram does not support any half - clock latencies. the overall read latency (rl) is defined as additive latency (al) + cas latency (cl); rl = al + cl. for more information on the supported cl and al settings based on the operating clock frequency, refer to standard speed bins . 2 . 3 .2. 3 test mode the normal operating mode is selected by mr0 (bit a7 = 0) and all other bits set to the desired values shown in figure 2.3.2 . programming bit a7 to a 1 places the ddr3 sdram into a test mode that is only used by the dram manufacturer an d should not be used. no operations or functionality is specified if a7 = 1. 2.3.2 .4 dll reset the dll reset bit is self - clearing, meaning that it returns back to the value of 0 after the dll reset function has been issued. once the dll is enabled, a su bsequent dll reset should be applied. any time that the dll reset function is used, tdllk must be met before any functions that require the dll can be used (i.e., read commands or odt synchronous operations).
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 12 rev. c 1 11/12 /2014 2.3.2 .5 write recovery the programmed wr valu e mr0 (bits a9, a10, and a11) is used for the auto precharge feature along with trp to determine tdal. wr (write recovery for auto - precharge) min in clock cycles is calculated by dividing twr (in ns) by tck (in ns) and rounding up to the next integer: wrmi n[cycles] = roundup(twr[ns]/tck[ns]). the wr must be programmed to be equal to or larger than twr(min). 2.3.2 .6 precharge pd dll mr0 (bit a12) is used to select the dll usage during precharge power - down mode. when mr0 (a12 = 0), or slow - exit, the dll is frozen after entering precharge power - down (for potential power savings) and upon exit requires txpdll to be met prior to the next valid command. when mr0 (a12 = 1), or fast - exit, the dll is maintained after entering precharge power - down and upon exitin g power - down requires txp to be met prior to the next valid command. 2.3 .3 mode register mr1 the mode register mr1 stores the data for enabling or disabling the dll, output driver strength, rtt_nom impedance, additive latency, write leveling enable, tdqs enable and qoff. the mode register 1 is written by asserting low on cs#, ras#, cas#, we#, high on ba0 and low on ba1 and ba2, while controlling the states of address pins according to figure 2.3.3 . * 1 : a8, a10, and a13 must be pr ogrammed to 0 during mrs. * tdqs must be disabled for x16 option. figure 2.3.3 mr1 definition ba2 ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 0 1 0* 1 qoff tdqs 0* 1 rtt 0* 1 level rtt d.i.c al rtt d.i.c dll mode register 1 a11 tdqs enable a7 write leveling enable a9 a6 a2 rtt_nom *3 a0 dll enable 0 disabled 0 disabled 0 0 0 odt disabled 0 enable 1 enabled 1 enabled 0 0 1 rzq/4 1 disable 0 1 0 rzq/2 a4 a3 additive latency 0 1 1 rzq/6 0 0 0 (al disabled) 1 0 0 rzq/12 *4 0 1 cl - 1 1 0 1 rzq/8 *4 1 0 cl - 2 1 1 0 reserved 1 1 reserved 1 1 1 reserved note: rzq = 240 ? a12 qoff *2 *3:in write leveling mode (mr1[bit7] = 1) with 0 output buffer enabled mr1[bit12]=1, all rtt_nom settings are allowed; in 1 output buffer disabled *2 write leveling mode (mr1[bit7] = 1) with *2: outputs disabled - dqs, dqss, dqs#s. mr1[bit12]=0, only rtt_nom settings of rzq/2, rzq/4 and rzq/6 are allowed. ba1 ba0 mr select *4:if rtt_nom is used during writes, only the 0 0 mr0 values rzq/2, rzq/4 and rzq/6 are allowed. 0 1 mr1 1 0 mr2 a5 a1 output driver impedance control 1 1 mr3 0 0 rzq/6 0 1 rzq/7 1 0 rzq/tbd 1 1 rzq/tbd
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 13 rev. c 1 11/12 /2014 2.3.3.1 dll enable/disable the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon returning to normal operation after having the dll disabled. during normal operation (dll - on) with mr1 (a0 = 0), the dll is automatically disabled when entering self - refresh operation and is automatically re - enabled upon exit of self - refresh operation. any time the dll is enabled and subsequently reset, tdllk clock cycles must occur before a read or synchronous odt command can be issued to allow tim e for the internal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in a violation of the tdqsck, taon or taof parameters. during tdllk, cke must continuously be registered high. ddr3 sdram does not require dll for any write operation, except when rtt_wr is enabled and the dll is required for proper odt operation. for more detailed information on dll disable operation re fer to dll - off mode . the direct odt feature is not supported during dll - off mode. the on - die termination resistors must be disabled by continuously registering the odt pin low and/or by programming the rtt_nom bits mr1{a9,a6,a2} to {0,0,0} via a mode register set command during dll - off mode. the dynamic odt feature is not support ed at dll - off mode. user must use mrs command to set rtt_wr, mr2 {a10, a9} = {0,0}, to disable dynamic odt externally. 2.3.3. 2 output driver impedance control the output driver impedance of the ddr3 sdram device is selected by mr1 (bits a1 and a5) as shown in figure 2.3.3 . 2.3.3 .3 odt rtt values ddr3 sdram is capable of providing two different termination values (rtt_nom and rtt_wr). the nominal termination value rtt_nom is programmed in mr1. a separate value (rtt_wr) may be programmed in mr2 to enabl e a unique rtt value when odt is enabled during writes. the rtt_wr value can be applied during writes even when rtt_nom is disabled. 2.3.3 .4 additive latency (al) additive latency (al) operation is supported to make command and data bus efficient for sust ainable bandwidths in ddr3 sdram. in this operation, the ddr3 sdram allows a read or write command (either with or without auto - precharge) to be issued immediately after the active command. the command is held for the time of the additive latency (al) befo re it is issued inside the device. the read latency (rl) is controlled by the sum of the al and cas latency (cl) register settings. write latency (wl) is controlled by the sum of the al and cas write latency (cwl) register settings. a summary of the al reg ister options are shown in table below . a4 a3 additive latency (al) settings 0 0 0 (al disabled) 0 1 cl - 1 1 0 cl - 2 1 1 reserved note: al has a value of cl - 1 or cl - 2 as per the cl values programmed in the mr0 register . 2.3.3.5 write leveling for better signal integrity, ddr3 memory module adopted fly - by topology for the commands, addresses, control signals, and clocks. the fly - by topology has the benefit of reducing the number of stubs and their length, but it also causes flight time skew betw een clock and strobe at every dram on the dimm. this makes it difficult for the controller to maintain tdqss, tdss, and tdsh specification. therefore, the ddr3 sdram supports a write leveling feature to allow the controller to compensate for skew. 2.3. 3.6 output disable the ddr3 sdram outputs may be enabled/disabled by mr1 (bit a12) as shown in figure 2.3.3. when this feature is enabled (a12 = 1), all output pins (dqs, dqs, dqs#, etc.) are disconnected from the device, thus removing any loading of the o utput drivers. this feature may be useful when measuring module power, for example. for normal operation, a12 should be set to 0.
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 14 rev. c 1 11/12 /2014 2.3.3.7 tdqs, tdqs# tdqs (termination data strobe) is a feature of x8 ddr3 sdram that provides additional termination resis tance outputs that may be useful in some system configurations. the tdqs function is available in x8 ddr3 sdram only and must be disabled via the mode register a11 =0 in mr1 for x16 configuration . 2.3 .4 mode register mr2 the mode register mr2 stores the data for controlling refresh related features, rtt_wr impedance, and cas write latency. the mode register 2 is written by asserting low on cs#, ras#, cas#, we#, high on ba1 and low on ba0 and ba2, while controlling the states of address pins according to t he below. * 1 : a5, a8, a11 ~ a13 must be programmed to 0 during mrs. * 2 : the rtt_wr value can be applied during writes even when rtt_nom is disabled. during write leveling, dynamic odt is not availa ble . figure 2.3.4 mr2 definition 2.3 .4.1 partial array self - refresh (pasr) if pasr (partial array self - refresh) is enabled, dat a located in areas of the array beyond the specified address range shown in figure 2.3 .4 will be lost if self - refresh is entered. data integrity will be maintained if trefi conditions are met and no self - refresh command is issued. 2.3 .4.2 cas write latenc y (cwl) the cas write latency is defined by mr2 (bits a3 - a5), as shown in figure 2.3 .4. cas write latency is the delay, in clock cycles, between the internal write command and the availability of the first bit of input data. ddr3 sdram does not support any half - clock latencies. the overall write latency (wl) is defined as additive latency (al) + cas write latency ba2 ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 1 0 0* 1 rtt_wr 0* 1 srt asr cwl pasr mode register 2 a7 self - refresh temperature (srt) range a2 a1 a0 partial array self - refresh (optional) 0 normal operating temperature range 0 0 0 full array 1 extended operating temperature range 0 0 1 halfarray (ba[2:0]=000,001,010, &011) 0 1 0 quarter array (ba[2:0]=000, & 001) 0 1 1 1/8th array (ba[2:0] = 000) a6 auto self - refresh (asr) 1 0 0 3/4 array (ba[2:0] = 010,011,100,101,110, & 111) 0 manual sr reference (srt) 1 0 1 halfarray (ba[2:0] = 100, 101, 110, &111) 1 asr enable 1 1 0 quarter array (ba[2:0]=110, &111) 1 1 1 1/8th array (ba[2:0]=111) a10 a9 rtt_wr *2 a5 a4 a3 cas write latency (cwl) 0 0 dynamic odt off (write does not affect rtt value) 0 0 0 5 (tck(avg) ? 2.5 ns) 0 1 rzq/4 0 0 1 6 (2.5 ns > tck(avg) ? 1.875 ns) 1 0 rzq/2 0 1 0 7 (1.875 ns > tck(avg) ? 1.5 ns) 1 1 reserved 0 1 1 8 (1.5 ns > tck(avg) ? 1.25 ns) 1 0 0 9 (1.25 ns > tck(avg) ? 1.07ns) ba1 ba0 mr select 1 0 1 10 (1.07 ns > tck(avg) ? 0.935 ns) 0 0 mr0 1 1 0 11 (0.935 ns > tck(avg) ? 0.833 ns) 0 1 mr1 1 1 1 12 (0.833 ns > tck(avg) ? 0.75 ns) 1 0 mr2 1 1 mr3
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 15 rev. c 1 11/12 /2014 (cwl); wl = al + cwl. for more information on the supported cwl and al settings based on the operating clock frequency, refer to standard speed b ins. 2.3 .4.3 auto self - refresh (asr) and self - refresh temperature (srt) for more details refer to extended temperature usage . ddr3 sdrams support self - refresh operation at all supported temperatures. applications requiring self - refresh operation in the extended temperature range must use the asr function or program the srt bit appropriately. 2.3 .4.4 dynamic odt (rtt_wr) ddr3 sdram introduces a new feature dynamic odt. in certain application cases and to further enhance signal integrity on the data b us, it is desirable that the termination strength of the ddr3 sdram can be changed without issuing an mrs command. mr2 register locations a9 and a10 configure the dynamic odt setings. in write leveling mode, only rtt_nom is available. for details on dynami c odt operation, refer to dynamic odt. 2.3 .5 mode register mr3 the mode register mr3 controls multi - purpose registers. the mode register 3 is written by asserting low on cs#, ras#, cas#, we#, high on ba1 and ba0, and low on ba2 while controlling the st ates of address pins according to the below. * 1 : a3 - a13 must be programmed to 0 during mrs. * 2 : the predefined pattern will be used for read synchronization. * 3 : when mpr control is set for normal operation (mr3 a[2] = 0) then mr3 a[1:0] will be ignored . figure 2.3.5 mr3 definition 2.3.5.1 multi - purpose register (mpr) the multi purpose register (mpr) function is used to read out a predefined system timing calibration bit sequence. to enable the mpr, a mode register set (mrs) command must be issued to mr3 register with bit a2=1. prior to issuing the mrs command, all banks must be in the idle state (all banks precharged and trp met). once the mpr is enabled, any subsequent rd or rda commands will be redirected to the multi purpose register. when the mpr is enabled, only rd or rda commands are allowed until a subsequent mrs command is issued with the mpr disabled (mr3 bit a2=0). power down mode, self - refresh and any other non - rd/rda command is not allowed during mpr enable mode. the reset function is supported during mpr enable mode. the multi purpose register (mpr) function is used to read out a predefined system timing calibration bit sequence. the basic concept of the mpr is shown in figure 2.3.5.1 . ba2 ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 1 1 0* 1 mpr mpr loc mode register 3 mrp operation mpr address a2 mpr a1 a0 mpr location 0 normal operation *3 0 0 predefined pattern *2 1 dataflow from mpr 0 1 rfu 1 0 rfu 1 1 rfu ba1 ba0 mr select 0 0 mr0 0 1 mr1 1 0 mr2 1 1 mr3
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 16 rev. c 1 11/12 /2014 figure 2.3.5.1 mpr block diagr am to enable the mpr, a mode register set (mrs) command must be issued to mr3 register with bit a2 = 1. prior to issuing the mrs command, all banks must be in the idle state (all banks precharged and trp met). once the mpr is enabled, any subsequent rd or rda commands will be redirected to the multi purpose register. the resulting operation, when a rd or rda command is issued, is defined by mr3 bits a [1:0] when the mpr is enabled . when the mpr is enabled, only rd or rda commands are allowed until a subsequent mrs command is issued with the mpr disabled (mr3 bit a2 = 0). note that in mpr mode rda has the same functionality as a read command whic h means the auto precharge part of rda is ignored. power - down mode, self - refresh and any other non - rd/rda command is not allowed during mpr enable mode. the reset function is supported during mpr enable mode. mpr mr3 register definition mr3 a[2] mr3 a[1:0] function mpr mpr - loc 0b dont care (0b or 1b) normal operation, no mpr transaction. all subsequent reads will come from dram array. all subsequent write will go to dram array. 1b see mpr definition table enable mpr mode, subsequent rd/rda commands defined by mr3 a[1:0]. memory core (all banks precharged) multipurpose register pre - defined data for read mr3[a2] dq, dm, dqs, dqs#
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 17 rev. c 1 11/12 /2014 mpr register address definition the following table provides an overview of the available data locations, how they are addressed by mr3 a[1:0] dur ing a mrs to mr3, and how thei r individual bits are mapped into the burst order bits during a multi purpose register read. mpr mr3 register definition mr3 a[2] mr3 a[1:0] function burst length read address a[2:0] burst order and data pattern 1b 00b read predefined pattern for system calibration bl8 000b burst order 0,1,2,3,4,5,6,7 pre - defined data pattern [0,1,0,1,0,1,0,1] bc4 000b burst order 0,1,2,3 pre - defined data pattern [0,1,0,1] bc4 100b burst order 4,5,6,7 pre - defined data pattern [0,1,0,1] 1b 01b rfu bl8 000b burst order 0,1,2,3,4,5,6,7 bc4 000b burst order 0,1,2,3 bc4 100b burst order 4,5,6,7 1b 10b rfu bl8 000b burst order 0,1,2,3,4,5,6,7 bc4 000b burst order 0,1,2,3 bc4 100b burst order 4,5,6,7 1b 11b rfu bl8 000b burst order 0,1,2,3,4,5,6,7 bc4 000b burst order 0,1,2,3 bc4 100b burst order 4,5,6,7 note: burst order bit 0 is assigned to lsb and the burst order bit 7 is assigned to msb of the selected mpr agent mpr functional description ? one bit wide logical interface via all dq pins during read operation. ? register read on x16: o dql[0] and dqu[0] drive information from mpr. o dql[7:1] and dqu[7:1] either drive the same information as dql[0], or they drive 0b. ? addressing during for multi purpose register reads for all mpr agents: o ba[2:0]: dont care o a[1:0]: a[1:0] must be equal to 00b. data read burst order in nibble is fixed o a[2]: for bl=8, a[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *) for burst chop 4 cases, the burst order is switched on nibble base a[2]=0b, b urst order: 0,1,2,3 *) a[2]=1b, burst order: 4,5,6,7 *) o a[9:3]: dont care o a10/ap: dont care o a12/bc: selects burst chop mode on - the - fly, if enabled within mr0. o a11, a13 : dont care ? regular interface functionality during register reads: o support two burst o rdering which are switched with a2 and a[1:0]=00b. o support of read burst chop (mrs and on - the - fly via a12/bc) o all other address bits (remaining column address bits including a10, all bank address bits) will be ignored by the ddr3 sdram. o regular read latenc ies and ac timings apply. o dll must be locked prior to mpr reads. note: *) burst order bit 0 is assigned to lsb and burst order bit 7 is assigned to msb of the selected mpr agent. note: good reference for the example of mpr feature is the jedec standard no. 93 - 3d, 4.10.4 protocol example .
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 18 rev. c 1 11/12 /2014 relevant timing parameters ac timing parameters are important for operating the multi purpose register: trp, tmrd, tmod, and tmprr. for more details refer to electrical characteristics & ac timing
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 19 rev. c 1 11/12 /2014 2.4 ddr3 sdram command description and operation 2.4.1 command truth table [ba=bank address, ra=row address, ca=column address, bc#=burst chop, x=dont care, v=valid] function abbreviation cke cs# ras# cas# we# ba0 - ba 2 a11, a13 a12/ bc# a10/ ap a0 - a9 notes previous cycle current cycle mode register set mrs h h l l l l ba op code refresh ref h h l l l h v v v v v self refresh entry sre h l l l l h v v v v v 7,9,12 self refresh exit srx l h h x x x x x x x x 7,8,9, 12 l h h h v v v v v single bank precharge pre h h l l h l ba v v l v precharge all banks prea h h l l h l v v v h v bank activate act h h l l h h ba row address(ra) write (fixed bl8 or bc4) wr h h l h l l ba rfu v l ca write (bc4, on the fly) wrs4 h h l h l l ba rfu l l ca write (bl8, on the fly) wrs8 h h l h l l ba rfu h l ca write with auto precharge (fixed bl8 or bc4) wra h h l h l l ba rfu v h ca write with auto precharge (bc4, on the fly) wras4 h h l h l l ba rfu l h ca write with auto precharge (bl8, on the fly) wras8 h h l h l l ba rfu h h ca read (fixed bl8 or bc4) rd h h l h l h ba rfu v l ca read (bc4, on the fly ) rds4 h h l h l h ba rfu l l ca read (bl8, on the fly) rds8 h h l h l h ba rfu h l ca read with auto precharge (fixed bl8 or bc4) rda h h l h l h ba rfu v h ca read with auto precharge (bc4, on the fly) rdas4 h h l h l h ba rfu l h ca read with auto precharge (bl8, on the fly) rdas8 h h l h l h ba rfu h h ca no operation nop h h l h h h v v v v v 10 device deselected des h h h x x x x x x x x 11 power down entry pde h l l h h h v v v v v 6,12 h x x x x x x x x power down exit pdx l h l h h h v v v v v 6,12 h x x x x x x x x zq calibration long zqcl h h l h h l x x x h x zq calibration short zqcs h h l h h l x x x l x notes: 1. all ddr3 sdram commands are defined by states of cs#, ras#, cas#, we# and cke at the rising edge of the clock. the msb of ba, ra and ca are device density and configuration dependant. 2. reset# is low enable command which will be used only for asynchronous reset so must be maintained high during any function. 3. bank addresses (ba) determine which bank is to be operated upon. for (e)mrs ba selects an (extended) mode register. 4. v means h or l (but a defined logic level) and x means either defined or undefined (like floating) logic level. 5. burst reads or writes cannot be terminated or interrupted and fixed/on - the - fly bl will be defined by mrs. 6. the power down mode does not perform any refresh operation. 7. the state of odt doe s not affect the states described in this table. the odt function is not available during self refresh. 8. self refresh exit is asynchronous. 9. vref(both vrefdq and vrefca) must be maintained during self refresh operation. vrefdq supply may be turned off and vr efdq may take any value between vss and vdd during self refresh operation, provided that vrefdq is valid and stable prior to cke going back high and that first write operation or first write leveling activity may not occur earlier than 512 nck after exit f rom self refresh. 10. the no operation command should be used in cases when the ddr3 sdram is in an idle or wait state. the purpose of the no operation command (nop) is to prevent the ddr3 sdram from registering any unwanted commands between operations. a no o peration command will not terminate a pervious operation that is still executing, such as a burst read or write cycle. 11. the deselect command performs the same function as no operation command. 12. refer to the cke truth table for more detail with cke transition .
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 20 rev. c 1 11/12 /2014 2.4.1 . cke truth table current state 2 cke command (n) 3 ras#, cas#, we#, cs# action (n) 3 notes previous cycle 1 (n - 1) current cycle 1 (n) power - down l l x maintain power - down 14,15 l h deselect or nop power - down exit 11,14 self - refresh l l x maintain self - refresh 15,16 l h deselect or nop self - refresh exit 8,12,16 bank(s) active h l deselect or nop active power - down entry 11,13,14 reading h l deselect or nop power - down entry 11,13,14,17 writing h l deselect or nop power - down entry 11,13,14,17 precharging h l deselect or nop power - down entry 11,13,14,17 refreshing h l deselect or nop precharge power - down entry 11 all bank idle h l deselect or nop precharge power - down entry 11,13,14,18 h l refresh self - refresh 9.13.18 notes: 1. cke (n) is the logic state of cke at clock edge n; cke (n - 1) was the state of cke at the previous clock edge. 2. current state is defined as the state of the ddr3 sdram immediately prior to clock edge n. 3. command (n) is the command registered at clock edge n, and action (n) is a result of command (n), odt is not included here. 4. all states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 5. the state of odt does not affect the states described in this table. the od t function is not available during self - refresh. 6. cke must be registered with the same value on tckemin consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the tckemin clocks of registeration. thus, after any cke transition, cke may not transition from its valid level during the time period of tis + tckemin + tih. 7. deselect and nop are defined in the command truth table. 8. on self - refresh exit deselect or nop commands must be issued on every clock edge occurring during the txs period. read or odt commands may be issued only after txsdll is satisfied. 9. self - refresh mode can only be entered from the all banks idle state. 10. must be a legal command as defined in the command truth table. 11. valid commands for power - down entry and exit are nop and deselect only. 12. valid commands for self - refresh exit are nop and deselect only. 13. self - refresh can not be entered during read or write operations. 14. the power - down does not perform any refresh operations. 15. x means dont care (including floating around vref) in self - refresh and power - down. it also applies to address pins. 16. vref (both vref_dq and vref_ca) must be maintained during self - refresh operation.vrefdq supply may be turned off and vrefdq may take any value between vss and vdd during self refresh operation, provided that vrefdq is valid and stable prior to cke going back high and that first write operation or first write leveling activity may not occur earlier than 512 nck after exit from self refresh. 17. if all banks are clos ed at the conclusion of the read, write or precharge command, then precharge power - down is entered, otherwise active power - down is entered. 18. idle state is defined as all banks are closed (trp, tdal, etc. satisfied), no data bursts are in progress, cke is high, and all timings from previous operations are satisfied (tmrd, tmod, trfc, tzqinit, tzqoper, tzqcs, etc.) as well as all self - refresh exit and power - down exit parameters are satisfied (txs, txp, txpdll, etc). 2.4.2 no operation (nop) command the no operation (nop) command is used to instruct the selected ddr3 sdram to perform a nop ( cs# low and ras#,cas#,we# high). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. 2.4. 3 deselect (des) command the deselect function ( cs# high) prevents new commands from being executed by the ddr3 sdram. the ddr3 sdram is effectively deselected. operations already in progress are not affected.
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 21 rev. c 1 11/12 /2014 2.4. 4 dll - off mode ddr3 dll - off mode is entered by setting mr1 bit a0 to 1; this will disable the dll for subsequent operations until a0 bit set back to 0. the mr1 a0 bit for dll control can be switched either during initialization or later. the dll - off mode operations listed below are an op tional feature for ddr3. the maximum clock frequency for dll - off mode is specified by the parameter tckdll_off. there is no minimum frequency limit besides the need to satisfy the refresh interval, trefi. due to latency counter and timing restrictions, onl y one value of cas latency (cl) in mr0 and cas write latency (cwl) in mr2 are supported. the dll - off mode is only required to support setting of both cl=6 and cwl=6. dll - off mode will affect the read data clock to data strobe relationship (tdqsck) but not the data strobe to data relationship (tdqsq, tqh). special attention is needed to line up read data to controller time domain. comparing with dll - on mode, where tdqsck starts from the rising clock edge (al+cl) cycles after the read command, the dll - off mod e tdqsck starts (al+cl - 1) cycles after the read command. another difference is that tdqsck may not be small compared to tck (it might even be larger than tck) and the difference between tdqsckmin and tdqsckmax is significantly larger than in dll - on mode. t he timing relations on dll - off mode read operation have shown at the following timing diagram (cl=6, bl=8) note: the tdqsck is used here for dqs, dqs, and dq to have a simplified diagram; the dll_off shift will affect both timings i n the same way and the skew between all dq, dqs, and dqs# signals will still be tdqsq . figure 2.4.4 dll - off mode read timing operation ck# ck command address dqs,dqs#(dll_on) dq(dll_on) d qs,dqs#(dll_ off ) dq (dll_ off ) d qs,dqs#(dll_o ff ) dq (dll_o ff ) tdqsck(dll_off)_min tdqsck(dll_off)_m ax rl (dll_off) = al+(cl - 1) = 5 rl (dll_o n ) = al+cl = 6 (cl=6,al=0) cl=6 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 read nop nop nop nop nop nop nop nop nop nop don t care
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 22 rev. c 1 11/12 /2014 2.4. 5 dll on/off switching procedure ddr3 dll - off mode is entered by setting mr1 bit a0 to 1; this will disable the dll for subsequent operation until a0 bit set back to 0. 2.4. 5.1 dll on to dll off procedure to switch from dll on to dll off requires te frequency to be changed during self - refresh outlined in the following procedure: 1. starting from idle state (all banks pre - charged, all timing fulfill ed, and drams on - die termination resistors, rtt, must be in high impedance state before mrs to mr1 to disable the dll). 2. set mr1 bit a0 to 1 to disable the dll. 3. wait tmod. 4. enter self refresh mode; wait until (tcksre) satisfied. 5. change frequency, in guidan ce with input clock frequency change section. 6. wait until a stable clock is available for at least (tcksrx) at dram inputs. 7. starting with the self refresh exit command, cke must continuously be registered high until all tmod timings from any mrs command a re satisfied. in addition, if any odt features were enabled in the mode registers when self refresh mode was entered, the odt signal must continuously be registered low until all tmod timings from any mrs command are satisfied. if both odt features were di sabled in the mode registers when self refresh mode was entered, odt signal can be registered low or high. 8. wait txs, and then set mode registers with appropriate values (especially an update of cl, cwl, and wr may be necessary. a zqcl command may also be i ssued after txs). 9. wait for tmod, and then dram is ready for next command. 2.4.5.2 dll off to dll on procedure to switch from dll off to dll on (with required frequency change) during self - refresh: 1. starting from idle state (all banks pre - charged, all timings fulfilled and drams on - die termination resistors (rtt) must be in high impedance state before self - refresh mode is entered.) 2. enter self refresh mode, wait until tcksre satisfied. 3. change frequency, in guidance with "input clock frequency change" . 4. wait until a stable clock is available for at least (tcksrx) at dram inputs. 5. starting with the self refresh exit command, cke must continuously be registered high until tdllk timing from subsequent dll reset command is satisfied. in addition, if any odt features were enabled in the mode registers when self refresh mode was entered, the odt signal must continuously be registered low until tdllk timings from subsequent dll reset command is satisfied. if both odt features are disabled in the mode registers w hen self refresh mode was entered, odt signal can be registered low or high. 6. wait txs, then set mr1 bit a0 to 0 to enable the dll. 7. wait tmrd, then set mr0 bit a8 to 1 to start dll reset. 8. wait tmrd, then set mode registers with appropriate values (espec ially an update of cl, cwl and wr may be necessary. after tmod satisfied from any proceeding mrs command, a zqcl command may also be issued during or after tdllk.) 9. wait for tmod, then dram is ready for next command (remember to wait tdllk after dll reset b efore applying command requiring a locked dll!). in addition, wait also for tzqoper in case a zqcl command was issued.
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 23 rev. c 1 11/12 /2014 2.4.6. input clock frequency change once the ddr3 sdram is initialized, the ddr3 sdram requires the clock to be stable duri ng almost all states of normal operation. this means that, once the clock frequency has been set and is to be in the stable state, the clock period is not allowed to deviate except for what is allowed for by the clock jitter and ssc (spread spectrum cloc king) specifications. the input clock frequency can be changed from one stable clock rate to another stable clock rate under two conditions: (1) self - refresh mode and (2) precharge power - down mode. outside of these two modes, it is illegal to change the cl ock frequency. for the first condition, once the ddr3 sdram has been successfully placed in to self - refresh mode and tcksre has been satisfied, the state of the clock becomes a dont care. once a dont care, changing the clock frequency is permissible, provided the new clock frequency is stable prior to tcksrx. when entering and exiting self - refresh mode for the sole purpose of changing the clock frequency, the self - refresh entry and exit specifications must still be met . the ddr3 sdram input clock freq uency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade. any frequency change below the minimum operating frequency would require the use of dll_on - mode - > dll_off - mode transition sequen ce, refer to dll on/off switching procedure . the second condition is when the ddr3 sdram is in precharge power - down mode (either fast exit mode or slow exit mode). if the rtt_nom feature was enabled in the mode register prior to entering precharge powe r down mode, the odt signal must continuously be registered low ensuring rtt is in an off state. if the rtt_nom feature was disabled in the mode register prior to entering precharge power down mode, rtt will remain in the off state. the odt signal can be r egistered either low or high in this case. a minimum of tcksre must occur after cke goes low before the clock frequency may change. the ddr3 sdram input clock frequency is allowed to change only with in the minimum and maximum oper ating frequency specified for the particular speed grade. during the input clock frequency change, odt and cke must be held at stable low levels. once the input clock frequency is changed, stable new clocks must be provided to the dram tcksrx before precharge power - down may be exit ed; after precharge power - down is exited and txp has expired, the dll must be reset via mrs. depending on the new clock frequency, additional mrs commands may need to be issued to appropriately set the wr, cl, and cwl with cke continuously registered high. during dll re - lock period, odt must remain low and cke must remain high. after the dll lock time, the dram is read y to operate with new clock frequency. 2.4.7 write leveling for better signal integrity, the ddr3 memory module adopted fly - by topology fo r the commands, addresses, control signals, and clocks. the fly - by topology has benefits from reducing number of stubs and their length, but it also causes flight time skew between clock and strobe at every dram on the dimm. this makes it difficult for th e controller to maintain tdqss, tdss, and tdsh specification. therefore, the ddr3 sdram supports a write leveling feature to allow the controller to compensate for skew. the memory controller can use the write leveling feature and feedback from the dd r3 sdram to adjust the dqs - dqs# to ck - ck# relationship. the memory controller involved in the leveling must have adjustable delay setting on dqs - dqs# to align the rising edge of dqs - dqs# with that of the clock at the dram pin. the dram asynchronous ly feeds back ck - ck#, sampled with the rising edge of dqs - dqs#, through the dq bus. the controller repeatedly delays dqs - dqs# until a transition from 0 to 1 is detected. the dqs - dqs# delay established though this exercise would ensure tdqss specifi cation. besides tdqss, tdss and tdsh specification also needs to be fulfilled. one way to achieve this is to combine the actual tdqss in the application with an appropriate duty cycle and jitter on the dqs - dqs# signals. depending on the actual tdqss in the application, the actual values for tdqsl and tdqsh may have to be better than the absolute limits provided in the chapter "ac timing parameters" in order to satisfy tdss and tdsh specification. a conceptual timing of this scheme is shown in figure 2.4. 7 .
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 24 rev. c 1 11/12 /2014 figure 2.4.7 write leveling concept dqs - dqs# driven by the controller during leveling mode must be terminated by the dram based on ranks populated. similarly, the dq bus driven by the dram must also be terminated at the controller. one or more data bits carry the leveling feedback to the controller across the dram configurations x8 and x16. on a x16 device, both byte lanes should be leveled independently. therefore, a separate feedback mechanism should be available for each byte lane. the upper da ta bits should provide the feed back of the upper diff_dqs(diff_udqs) to clock relationship whereas the lower data bits would indicate the lower diff_dqs(diff_ldqs) to clock relationship. 2.4.7 .1 dram setting for write level ing & dram termination function in that mode dram enters into write leveling mode if a7 in mr1 set high and after finishing leveling, dram exits from write leveli ng mode if a7 in mr1 set low . note that in write leveling mode, only dqs/dqs# termination s are activated and deactivated via odt pin, un like normal operation . mr setting involved in the leveling procedure function mr1 enable disable write leveling enable a7 1 0 output buffer mode (qoff) a12 0 1 dram termination function in the leveling mode odt pin @dram dqs/dqs# termination dqs termination de - asserted off off asserted on off note: in write leveling mode with its output buffer disabled (mr1[bit7] = 1 with mr1[bit12] = 1) all rtt_nom settings are all owed; in write leveling mode with its output buffer enabled (mr1[bit7] = 1 with mr1[bit12] = 0) only rtt_nom settings of rzq/2, rzq/4 and rzq/6 are allowed. ck# ck diff_dqs source destination ck# ck diff_dqs dq diff_dqs dq push dqs to capture 0 - 1 transition 0 or 1 0 0 0 0 or 1 1 1 1 t0 t1 t2 t3 t4 t5 t6 t7 t0 t1 t2 t3 t4 t5 t6 tn
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 25 rev. c 1 11/12 /2014 2.4.7 .2 procedure description the memory controller initiates leveling mode of all drams by setting bit 7 of mr1 to 1. when entering write leveling mode, the dq pins are in undefined driving mode. during write leveling mode, only nop or deselect commands are allowed, as well as an mrs command to exit write leveling mode. since the controller levels one rank at a time, the output of other ranks must be disabled by setting mr1 bit a12 to 1. the controller may assert odt after tmod, at which time the dram is ready to accept the odt signal . the controller may drive dqs low and dqs# high after a delay of twldqsen, at which time the dram has applied on - die termination on these signals. after tdqsl and twlmrd , the controller provides a sin gle dqs, dqs# edge which is used by the dram to sample ck - ck# driven from controller. twlmrd(max) timing is controller dependent. dram samples ck - ck# status with rising edge of dqs - dqs# and provides feedback on the dq b u s asynchronously after twlo timing. in this product, the dq0 for x8 or dq0 and dq8 for x16 ("prime dq bit(s)") provide the leveling feedback. the dram's remaining dq bits are driven low statically after the first sampling procedure. there is a dq output uncertainty of twloe defined to allow mismatch on dq bits. the twloe period is define d from the transition of the earliest dq bit to the corresponding transition of the latest dq bit. there are no read strobes (dqs/dqs#) needed for these dqs. controller samples incoming dq and decides to increment or decrement dqs - dqs# delay setting and launches the next dqs/dqs# pulse after some time, which is controller dependent. once a 0 to 1 transition is detected, the controller locks dqs - dqs# delay setting and write leveling is achieved for the device. figure 2.4.7 .2 describes the timing diagram and parameters for the overall write leveling procedure. notes: 1. the jedec specification for ddr3 dram has the option to drive leveling feedback on a single prime dq or all dqs. for best compatibility with future ddr3 products, applications should use the lowest order dq for each byte lane (dq0 for x8, or dq0 and dq8 for x16). 2. mrs: load mr1 to enter write leveling mode. 3. nop: nop or deselect. 4. diff_dqs is the differential data strobe (dqs, dqs#). timing reference points are the zero crossings. dqs is shown with solid line, dq s# is shown with dotted line. 5. ck, ck# : ck is shown with solid dark line, where as ck# is drawn with dotted line. 6. dqs, dqs# needs to fulfill minimum pulse width requirements tdqsh(min) and tdqsl(min) as defined for regular writes; the max pulse width is system dependent. ck# (5 ) ck cmd mrs nop nop tmod nop nop nop t1 twlh twls t2 twlh twls nop nop nop nop nop nop don t care undefined driving mode time break odt diff_dqs (4 ) prime dq (1) late remaining dqs early remaining dqs (2) (3) twldqsen tdqsl (6) tdqsh (6) tdqsl (6) tdqsh (6) twlmrd twlo twlo twlo twlo twloe figure 2.4.7.2 write leveling sequence [dqs - dqs# is capturing ck - ck# low at t1 and ck - ck# high at t2]
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 26 rev. c 1 11/12 /2014 2.4.7 . 3 write leveling mode exit the following sequence describes how the write leveling mode sh ould be exited: 1. after the last rising strobe edge, stop driving the strobe sign als. note: from now on, dq pins are in undefined driving mode, and will remain undefined, u ntil tmod after the respective mr command. 2. drive odt pin low (tis must be satisfie d) and continue registering low. 3. after the rtt is switched off, disable write level mode via mrs command. 4. after tmod is satisfied , any valid command may be registered. (mr commands may be issued after tmrd ). 2.4.8 extended temperature usage a. auto s elf - refresh supported b. extended temperature range supported c. double refresh required for operation in the extended temperature range (applies only for devices supporting the extended temperature range) mode register description field bits description au to self - refresh (asr) when enabled, ddr3 sdram automatically provides self - refresh power management functions for all supported operating temperature values. if not enabled, the srt bit must be programmed to indicate toper asr mr2 (a6) during subsequent self - refresh operation 0 = manual sr reference (srt) 1 = asr enable self - refresh temperature (srt) range if asr = 0, the srt bit must be programmed to indicate toper during subsequent self - refresh operation srt mr2 (a7) if asr = 1, srt bit must be set to 0b 0 = normal operating temperature range 1 = extended operating temperature range 2.4.8 . 1 auto self - re fresh mode - asr mode ddr3 sdram provides an auto self - refresh mode (asr) for application ease. asr mode is enabled by setting mr2 bit a6 = 1b and mr2 bit a7 = 0b. the dram will manage self - refresh entry in either the normal or extended (optional) temperature ranges. in this mode, the dram will also manage self - refresh power consumption when the dram operating temperature changes, lower at low temperatures and higher at high temperatures. if the asr option is not supported by the dram, mr2 bit a6 must be set to 0b. if the asr mode is not enabled (mr2 bit.a6 = 0b), the srt bit (mr2 a7) must be manually programmed with the operating temperature range required during self - refresh operation. support of the asr option does not automatically imply support of the extended temperature range. refer to operating temperature range for restrictions on operating conditions.
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 27 rev. c 1 11/12 /2014 2.4.8. 2 self - refresh temperature range - srt srt applies to devices supporting extended temperature range only. if asr = 0b, the self - refresh temperature (srt) range bit must be programmed to guarantee proper self - refresh operation. if srt = 0b, then the dram will set an appropriate refresh rate for self - refresh operation in the normal temperature range. if srt = 1b then the dram will set an appropriate, potentially different, refresh rate to allow self - refresh operation in either the normal or extended temperature ranges. the value of the srt bit can effect self - refresh power consumption, please refer to the idd table for details. for parts that do not support the extended temperature range, mr2 bit a7 must be set to 0b and the dram should not be operated outside t he normal temperature range. self - refresh mode summary mr2 a[6] mr2 a[7] self - refresh operation allowed operating temperature range for self - refresh mode 0 0 self - refresh rate appropriate for the normal temperature range normal (0 to 85 o c) 0 1 self - refresh rate appropriate for either the normal or extended temperature ranges. the dram must support extended temperature range . the value of the srt bit can a ffect self - refresh power consumption, please refer to the idd table for details. normal (0 t o 8 5 o c) a nd extended (85 to 95 o c) 1 0 asr enabled (for devices supporting asr and normal temperature range). self - refresh power consumption is temperature dependent normal (0 to 85 o c) 1 0 asr enabled (for devices supporting asr and extended temperature range). self - refresh power consumption is temperature dependent normal (0 to 8 5 o c) a nd extended (85 to 95 o c) 1 1 illegal
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 28 rev. c 1 11/12 /2014 3. absolute maximum rat ings and ac & dc operating co nditions 3.1 absolute maximum dc ratings. symbol parameter rating units note vdd voltage on vdd pin relative to vss - 0.4 v ~ 1.975 v v 1,3 vddq voltage on vddq pin relative to vss - 0.4 v ~ 1.975 v v 1,3 vin, vout voltage on any pin relative to vss - 0.4 v ~ 1.975 v v 1 tstg storage temperature - 55 to +1 5 0 c 1,2 notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability . 2. storage temperature is the case surface temperature on the center/top side of the dram. 3. vdd and vddq must be within 300 mv of each other at all times; and vref must be not greater than 0.6 x vddq, when vdd and vddq are less than 500 mv; vref may be equal to or less than 300 mv 3.2 component operating temperature range symbol parameter rating units notes t oper commercial tc = 0 to 85 c 1,2 tc = 85 to 95 c 1,3 industrial tc = - 4 0 to 85 c 1,2 tc = 85 to 95 c 1,3 automotive (a1) tc = - 4 0 to 85 c 1,2 tc = 85 to 95 c 1,3 automotive (a2) tc = - 4 0 to 85 c 1,2 tc = 85 to 95 c 1,3 tc = 95 to 105 c 1,4 notes: 1. operating temperature toper is the case surface temperature (tc) on the center / top side of the dram. 2. this t emper ature r ange specifies the temperatures where all dram specifications will be supported. during operation, the dram case temperature must be maintained in this range under all operating conditions . 3. some applications require operation of the dram in the extended temperature range ( 85 c < tc ? 9 5 c ) . full specifications are supported in this range, but the following additional conditions apply: a ) refresh commands must be doubled in frequency, therefore reducing the refresh interval trefi to 3.9 s. b ) if self - refresh operation is required for this range, it is mandatory to use either the manual self - refresh mode wi th extended temperature range capability (mr2 a6 = 0b and mr2 a7 = 1b) or enable the auto self - refresh mode (mr2 a6 = 1b and mr2 a7 = 0b ). 4. no type of self - refresh mode is supported for this range. 3.3 recommended dc operating conditions(sstl_1.5) symb ol parameter rating unit notes min typ max vdd supply voltage ddr3 1.425 1.5 1.575 v 1,2 ddr3l 1.283 1.35 1.45 v 3,4,5,6 ,7 vddq supply voltage for output ddr3 1.425 1.5 1.575 v 1,2 ddr3l 1.283 1.35 1.45 v 3,4,5,6 ,7 notes: 1. under all conditions vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters are measured with vdd and vddq tied together. 3. maximum dc value may not be greater than 1.425v. the dc value is the linear average of v dd /v dd (t) over a long period of ti me. 4. if the limit is exceeded, the input levels are covered by the ddr3 specification. 5. with these supply voltages, the device operates with ddr3l specifications. 6. after initialized for ddr3 operation, the ddr3l may be used only upon reset. 7. this ddr3l product supports 1.5v (ddr3) operation, and if initialized as such, retains the origin al speed timings defined for ddr3l speed option .
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 29 rev. c 1 11/12 /2014 3.4 thermal resistance package substrate theta - ja (airflow = 0m/s) theta - ja (airflow = 1 m/s) theta - ja (airflow = 2 m/s) theta - jc units 78 - ball 4 - layer 45.9 40.5 39.0 6.8 c/w 96 - ball 4 - layer 44.7 39.4 37.8 6.7 c/w 4. ac & dc input mea surement levels 4.1. ac and dc logic input levels for single - ended signals 4 . 1 .1 ac and dc input levels for single - ended command and address signals symbol parameter ddr3 - 800/1066/1333/1600 ddr3 - 1866/2133 units note min. max. min. max. v 1 vih.ca(dc100) dc input logic high vref + 0.100 v dd vref + 0.100 v dd v 1 vil.ca(dc100) dc input logic low v ss vref - 0.100 v ss vref - 0.100 v 1, 2, 5 vih.ca(ac175) ac input logic high vref + 0.175 note2 -- -- v 1, 2, 5 vil.ca(ac175) ac input logic low note2 vref - 0.175 -- -- v 1, 2, 5 vih.ca(ac150) ac input logic high vref + 0.150 note2 -- -- v 1, 2, 5 vil.ca(ac150) ac input logic low note2 vref - 0.150 -- -- v 1, 2, 5 vih.ca(ac135) ac input logic high -- -- vref + 0.135 note2 v 1, 2, 5 vil.ca(ac135) ac input logic low -- -- note2 vref - 0.135 v 1, 2, 5 vih.ca(ac125) ac input logic high -- -- vref + 0.125 note2 v 1, 2, 5 vil.ca(ac125) ac input logic low -- -- note2 vref - 0.125 v 1, 2, 5 vrefca(dc) reference voltage for add, cmd inputs 0.49 * v dd 0.51* v dd 0.49 * v dd 0.51* v dd v 3, 4 symbol parameter ddr3l - 800/1066/1333/1600 ddr3l - 1866 units note min. max. min. max. v 1 vih.ca(dc90) dc input logic high vref + 0.09 v dd vref + 0.09 v dd v 1 vil.ca(dc90) dc input logic low v ss vref - 0.09 v ss vref - 0.09 v 1, 2, 5 vih.ca(ac160) ac input logic high vref + 0.16 note2 -- -- v 1, 2, 5 vil.ca(ac160) ac input logic low note2 vref - 0.160 -- -- v 1, 2, 5 vih.ca(ac135) ac input logic high vref + 0.135 note2 vref + 0.135 note2 v 1, 2, 5 vil.ca(ac135) ac input logic low note2 vref - 0.135 note2 vref - 0.135 v 1, 2, 5 vih.ca(ac125) ac input logic high -- -- vref + 0.125 note2 v 1, 2, 5 vil.ca(ac125) ac input logic low -- -- note2 vref - 0.125 v 1, 2, 5 vrefca(dc) reference voltage for add, cmd inputs 0.49 * v dd 0.51* v dd 0.49 * v dd 0.51* v dd v 3, 4 notes: 1. for input only pins except reset.vref=vrefca(dc) 2. see "overshoot and undershoot specifications" 3. the ac peak noise on vref may not allow vref to deviate from vref(dc) by more than +/ - 1.0 % vdd. 4. for reference: ddr3 has approx. v dd /2 +/ - 15mv, ddr3l has approx v dd /2 +/ - 13.5mv. 5. to allow vrefca margining, all dram com mand and address input buffers must use external vref (provided by system) as the input for their vrefca pins. all vih/l input level must be compared with the external vref level at the 1st stage of the command and address input buffer
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 30 rev. c 1 11/12 /2014 4 . 1 .2 ac and dc logic input levels for single - ended signals & dq and dm symbol parameter ddr3 - 800/1066 ddr3 - 1333/1600 ddr3 - 1866/2133 units note min. max. min. max. min. max. v 1 vih.dq(dc100) dc input logic high vref + 0.100 v dd vref + 0.100 v dd vref + 0.100 v dd v 1 vil.dq(dc100) dc input logic low v ss vref - 0.100 v ss vref - 0.100 v ss vref - 0.100 v 1, 2, 5 vih.dq(ac175) ac input logic high vref + 0.175 note2 -- -- -- -- v 1, 2, 5 vil.dq(ac175) ac input logic low note2 vref - 0.175 -- -- -- -- v 1, 2, 5 vih.dq(ac150) ac input logic high vref + 0.150 note2 vref + 0.150 note2 -- -- v 1, 2, 5 vil.dq(ac150) ac input logic low note2 vref - 0.150 note2 vref - 0.150 -- -- v 1, 2, 5 vih.dq(ac135) ac input logic high vref + 0.135 note2 vref + 0.135 note2 vref + 0.135 note2 v 1, 2, 5 vil.dq(ac135) ac input logic low note2 vref - 0.135 note2 vref - 0.135 note2 vref - 0.135 v 1, 2, 5 vrefdq(dc) reference voltage for dq, dm inputs 0.49 * v dd 0.51* v dd 0.49 * v dd 0.51* v dd 0.49 * v dd 0.51* v dd v 3, 4
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 31 rev. c 1 11/12 /2014 symbol parameter ddr3l - 800/1066 ddr3l - 1333/1600 ddr3l - 1866 units note min. max. min. max. min. max. v 1 vih.dq(dc90) dc input logic high vref + 0.09 v dd vref + 0.09 v dd vref + 0.09 v dd v 1 vil.dq(dc90) dc input logic low v ss vref - 0.09 v ss vref - 0.09 v ss vref - 0.09 v 1, 2, 5 vih.dq(ac160) ac input logic high vref + 0.16 note2 vref + 0.16 note2 -- -- v 1, 2, 5 vil.dq(ac160) ac input logic low note2 vref - 0.16 note2 vref - 0.16 -- -- v 1, 2, 5 vih.dq(ac135) ac input logic high vref + 0.135 note2 vref + 0.135 note2 vref + 0.135 note2 v 1, 2, 5 vil.dq(ac135) ac input logic low note2 vref - 0.135 note2 vref - 0.135 note2 vref - 0.135 v 1, 2, 5 vih.dq(ac130) ac input logic high -- -- -- -- vref + 0.13 note2 v 1, 2, 5 vil.dq(ac130) ac input logic low -- -- -- -- note2 vref - 0.13 v 1, 2, 5 vrefdq(dc) reference voltage for dq, dm inputs 0.49 * v dd 0.51* v dd 0.49 * v dd 0.51* v dd 0.49 * v dd 0.51* v dd v 3, 4 notes: 1. for input only pins except reset#. vref = vrefdq(dc) 2. see "overshoot and undershoot specifications" 3. the ac peak noise on vref may not allow vref to deviat e from vref(dc) by more than 1.0 % vdd. 4. for reference: ddr3 has approx. vdd/2 15mv, and ddr3l has approx. v dd /2 13.5mv. 5. single - ended swin g requirement for dqs - dqs# , is 350mv (peak to peak). differential swing requirement for dqs - dqs# , is 700mv (peak to peak)
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 32 rev. c 1 11/12 /2014 4.2 vref tolerances the dc - tolerance limits and ac - moist limits for the reference voltages vrefca and vrefdq are illustrat ed in the following figure. it shows a valid reference voltage vref(t) as a function of time. (vref stands for vrefca and vrefdq likewise). vref(dc) is the linear average of vref(t) over a very long period of time (e.g.,1 sec). this average has to meet the min/max requirement in previous page. furthermore vref(t) may temporarily deviate from vref(dc) by no more than 1% vdd. the voltage levels for setup and hold time measurements vih(ac), vih(dc), vil(ac), and vil(dc) are dependent on vref. vref shall be understood as vref(dc). the clarifies that dc - variations of vref affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. system timing and voltage budgets need to ac count for vref(dc) deviations from the optimum position within the data - eye of the input signals. this also clarifies that the dram setup/hold specification and de - rating values need to include time and voltage associated with vref ac - noise. timing and vol tage effects due to ac - noise on vref up to the specified limit (1% of vdd) are included in dram timing and their associated de - ratings. figure 4.2 illustration of vref(dc) tolerance and vrefac - noise limits voltage vref(d c) vref ac - noise v ref(t ) vref(dc) max vref(dc) min vdd vss time
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 33 rev. c 1 11/12 /2014 4.3. ac and dc logic input levels for differential signals 4.3.1 differential signal definition figure 4.3.1 definition of differential ac - swing and time above ac - level 4.3.2 differential swing requirements for clock (ck - ck#) and strobe (dqs - dqs#) 1. differential ac and dc input levels symbol parameter ddr3 - 800, 1066, 1333, 1600 , 1866, 2133 unit notes min max vihdiff differential input logic high +0.200 note3 v 1 vildiff differential input logic low note3 - 0.200 v 1 vihdiff(ac) differential input high ac 2 x ( vih(ac) C vref ) note3 v 2 vildiff(ac) differential input low ac note3 2 x ( vref - vil(ac) ) v 2 symbol parameter ddr3l - 800, 1066, 1333, 1600 , 1866 unit notes min max vihdiff differential input logic high +0.180 note3 v 1 vildiff differential input logic low note3 - 0.180 v 1 vihdiff(ac) differential input high ac 2 x ( vih(ac) C vref ) note3 v 2 vildiff(ac) differential input low ac note3 2 x ( vref - vil(ac) ) v 2 notes: 1. used to define a differential signal slew - rate. 2. for ck - ck# use vih/vil(ac) of add/cmd and vrefca; for dqs - dqs#, dqsl, dqsl#, dqsu, dqsu# use vih/vil(ac) of dqs and vrefdq; if a reduced ac - high or ac - low level is used for a signal group, then the reduced level applies also here. 3. these values are not defined; however, the single - ended signals ck, ck#, dqs, dqs#, dqsl, dqsl#, dqsu, dqsu# need to be within the respective limits (vih(dc) max, vil(dc)min) for single - ended signals as well as the limitations for overshoot and undershoot . tdvac v ih.diff.ac.min v ih.diff.min v ih.diff.max v ih.diff.ac.max h alf cycle tdvac time differential input voltage (i.e. dqs C dqs # , ck C ck # )
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 34 rev. c 1 11/12 /2014 4.3.2.2 minimum required time bef ore ringback (tdvac) for ck - ck# and dqs - dqs# slew rate [v/ns] ddr3 - 800/1066/1333/1600 ddr3 - 1866/2133 tdvac [ps] @ |vih/ldiff(ac)| = 350mv tdvac [ps] @ |vih/ldiff(ac)| = 300mv tdvac [ps] @ |vih/ldiff(ac)| = (dqs - dqs#) only tdvac [ps] @ |vih/ldiff(ac)| = 300mv tdvac [ps] @ |vih/ldiff(ac)| = (ck - ck#) only > 4.0 75 175 214 134 139 4 57 170 214 134 139 3 50 167 191 112 118 2 38 119 146 67 77 1.8 34 102 131 52 63 1.6 29 81 113 33 45 1.4 22 54 88 9 23 1.2 note 19 56 note note 1 note note 11 note note < 1 note note note note note slew rate [v/ns] ddr3l - 800/1066/1333/1600 ddr3l - 1866 tdvac [ps] @ |vih/ldiff(ac)| = 320mv tdvac [ps] @ |vih/ldiff(ac)| = 270mv tdvac [ps] @ |vih/ldiff(ac)| = 270mv tdvac [ps] @ |vih/ldiff(ac)| = 250mv tdvac [ps] @ |vih/ldiff(ac)| = 260mv > 4.0 189 201 163 168 176 4 189 201 163 168 176 3 162 179 140 147 154 2 109 134 95 105 111 1.8 91 119 80 91 97 1.6 69 100 62 74 78 1.4 40 76 37 52 56 1.2 note 44 5 22 24 1 note note note note note < 1 note note note note note note: the rising input differential signal shall become equal to or greater than vihdiff(ac) level; and the falling input di fferential signal shall become equal to or less than vildiff(ac) level.
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 35 rev. c 1 11/12 /2014 4.3.3. single - ended requirements for differential signals each individual component of a differential signal (ck, dqs, dqsl, dqsu, ck#, dqs#, dqsl#, or dqsu#) has also to comply with certain requirements for single - ended signals. ck and ck# have to approximately reach vsehmin / vselmax (approximately equal to the ac - levels (vih(ac) / vil(ac) ) for add/cmd signals) in every half - cycle. dqs, dqsl, dqsu, dqs#, dqsl# have to reach vsehmin / vselmax (approximately the ac - levels (vih(ac) / vil(ac) ) for dq signals) in every h alf - cycle preceding and following a valid transition. 4.3.3.1. single - ended levels for ck, dqs, dqsl, dqsu, ck#, dqs#, dqsl# or dqsu# symbol parameter ddr3/ddr3l - 800, 1066, 1333, & 1600 unit notes min max vseh single - ended high - level for strobes (vddq/2) + 0.175 note3 v 1, 2 single - ended high - level for ck, ck (vddq/2) + 0.175 note3 v 1, 2 vsel single - ended low - level for strobes note3 (vddq/2) - 0.175 v 1, 2 single - ended low - level for ck, ck note3 (vddq/2) - 0.175 v 1, 2 notes: 1. for ck, ck# use vih/vil(ac) of add/cmd; for strobes (dqs, dqs#, dqsl, dqsl#, dqsu, dqsu#) use vih/vil(ac) of dqs. 2. vih(ac)/vil(ac) for dqs is based on vrefdq; vih(ac)/vil(ac) for add/cmd is based on vrefca; if a reduced ac - high or ac - low level is used for a signal grou p, then the reduced level applies also here 3. these values are not defined, however the single - ended signals ck, ck#, dqs, dqs#, dqsl, dqsl#, dqsu, dqsu# need to be within the respective limits (vih(dc) max, vil(dc)min) for single - ended signals as well as th e limitations for overshoot and undershoot. figure 4.3.3 single - ended requirement for differential signals. vss or vssq vselmax vdd/2 or vddq/2 vsehmin vsel vseh ck or dqs time vdd or vddq
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 36 rev. c 1 11/12 /2014 4.4 differential input cross point voltage to guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (ck, ck and dqs, dqs) must meet the requirements in the following table. the d ifferential input cross point voltage vix is measured from the actual cross point of true and completement signal to the midlevel between of vdd and vss. figure 4.4. vix definition 4.4.1 cross point voltage for differential input signals (ck, dqs) symbol parameter ddr3 - 800, 1066, 1333, 1600 , 1866, 2133 unit note min. max. vix differential input cross point voltage relative to vdd/2 for ck, ck - 150 150 mv - 175 175 mv 1 differential input cross point voltage relative to vdd/2 for dqs, dqs - 150 150 mv note: 1. extended range for vix is only allowed for clock and if single - ended clock input signals ck and ck# are monotonic with a single - ended swing vsel / vseh of at least vdd/2 +/ - 250 mv, and when the differential slew rate of ck - ck# is larger than 3 v/ns. 4 .5 slew rate definitions for single - ended input signals see address / command setup, hold and derating for single - ended slew rate definitions for address and command signals. see data setup, hold and slew rate derating for single - ended slew rate definitions for data signals. vdd ck#,dqs# vdd/2 ck,dqs vss v ix v ix v ix
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 37 rev. c 1 11/12 /2014 4.6. slew rate definition for differential input signals 4.6.1 differ ential input slew rate definition description measured defined by from to differential input slew rate for rising edge (ck - ck# & dqs - dqs#) vildiffmax vihdiffmin [vihdiffmin - vildiffmax] / deltatrdiff differential input slew rate for falling edge (ck - ck# & dqs - dqs#) vihdiffmin vildiffmax [vihdiffmin - vildiffmax] / deltatfdiff note : the differential signal (i.e., ck - ck# & dqs - dqs#) must be linear between these thresholds. figure 4.6.1 input nominal slew rate definition for dqs, dqs# and ck, ck# differential input voltage(i.e. dqs - dqs#, ck - ck#)
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 38 rev. c 1 11/12 /2014 5. ac and dc output mea surement levels 5.1 single ended ac and dc output levels symbol parameter value unit notes voh(dc) dc output high measurement level (for iv curve linearity) 0.8xvddq v vom(dc) dc output mid measurement level (for iv curve linearity) 0.5xvddq v vol(dc) dc output low measurement level (fro iv curve linearity) 0.2xvddq v voh(ac) ac output high measurement level (for output sr) vtt+0.1xvddq v 1 vol(ac) ac output low measurement level (for output sr) vtt - 0.1xvddq v 1 note 1. the swing of 0.1 vddq is based on approximately 50% of the static single - ended output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? t o vtt = vddq/2. 5.2 differential ac and dc output levels symbol parameter value unit notes vohdiff(ac) ac differential output high measurement level (for output sr) +0.2 x vddq v 1 voldiff(ac) ac differential output low measurement level (for output sr) - 0.2 x vddq v 1 note 1. the swing of 0.2 vddq is based on approximately 50% of the static single - ended output high or low swing with a driver impedance of 40 ? a nd an effective test load of 25 ? to vtt = vddq/2 at each of the differential outputs. 5.3 single ended output slew rate 5.3.1 single ended output slew rate definition description measured defined by from to single ended output slew rate for rising edge vol(ac) voh(ac) [voh(ac) - vol(ac)] / deltatrse single ended output slew rate for falling edge voh(ac) vol(ac) [voh(ac) - vol(ac)] / deltatfse figure 5.3.1 single ended output slew rate definition 5. 3.2 output slew rate (single - ended) parameter symbol ddr3 - 800 ddr3 - 1066 ddr3 - 1333 ddr3 - 1600 ddr3 - 1866 ddr3 - 2133 unit min. max. min. max. max. max. max. max. max. max. max. max. single - ended output slew rate ddr3 srqse 2.5 5 2.5 5 2.5 5 2.5 5 2.5 5 2.5 5 v/ns ddr3l 1.75 5 1.75 5 1.75 5 1.75 5 1.75 5 1.75 5 note: sr: slew rate. q: query output (like in dq, which stands for data - in, query - output). se: single - ended signals. for ron = rzq/7 setting. single ended output voltage(i.e. dq)
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 39 rev. c 1 11/12 /2014 5.4 differential output slew rate 5.4.1 differential output slew rate definition description measured defined by from to differential output slew rate for rising voldiff(ac) vohdiff(ac) [vohdiff(ac) - voldiff(ac)]/deltatrdiff differential output slew rate for falling vohdiff(ac) voldiff(ac) [vohdiff(ac) - voldiff(ac)]/deltatfdiff note: output slew rate is verified by design and characterization, and not 100% tested in production . figure 5.4.1 differential output slew rate definition 5.4.2 differential output slew rate parameter symbol ddr3 - 800 ddr3 - 1066 ddr3 - 1333 ddr3 - 1600 ddr3 - 1866 ddr3 - 2133 unit min. max. min. max. max. max. max. max. max. max. max. max. differential output slew rate ddr3 srqdiff 5 10 5 10 5 10 5 10 5 10 5 10 v/ns ddr3l 3.5 12 3.5 12 3.5 12 3.5 12 3.5 12 3.5 12 description: sr: slew rate, q: query output (like in dq, which stands for data - in, query - output), diff: differential signals, for ron = rzq/7 setting 5.5 reference load for ac timing and output slew rate the following figure represents the effective reference load of 25 ohms used in defining the relevant ac timing parameters of the device as well as output slew rate measurements. it is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. system designers should use ibis or other simulation tools to correlate the timing reference load to a system environment. manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester elect ronics. figure 5.5 reference load for ac timing and output slew rate ck,ck# dut dq, dqs, dqs# vddq 25ohm vtt=vddq/2 timing reference point
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 40 rev. c 1 11/12 /2014 5.6 overshoot and undershoot specifications 5.6.1 ac overshoot/undershoot specification for address and control pins item ddr3 - 800 ddr3 - 1066 ddr3 - 1333 ddr3 - 1600 ddr3 - 1866 ddr3 - 2133 units maximum peak amplitude allowed for overshoot area 0.4 0.4 0.4 0.4 0.4 0.4 v maximum peak amplitude allowed for undershoot area 0.4 0.4 0.4 0.4 0.4 0.4 v maximum overshoot area above vdd 0.67 0.5 0.4 0.33 0.28 0.25 v - ns undershoot area below vss 0.67 0.5 0.4 0.33 0.28 0.25 v - ns note : a0 - a1 3 , ba0 - ba 2 , cs#, ras#, cas#, we#, cke, odt 5.6.2 ac overshoot/undershoot specification for clock, data, strobe, and mask item ddr3 - 800 ddr3 - 1066 ddr3 - 1333 ddr3 - 1600 ddr3 - 1866 ddr3 - 2133 units maximum peak amplitude allowed for overshoot area 0.4 0.4 0.4 0.4 0.4 0.4 v maximum peak amplitude allowed for undershoot area 0.4 0.4 0.4 0.4 0.4 0.4 v maximum overshoot area above vdd 0.25 0.19 0.15 0.13 0.11 0.10 v - ns undershoot area below vss 0.25 0.19 0.15 0.13 0.11 0.10 v - ns note : ck, ck#, dq, dqs, dqs#, dm maximum amplitude overshoot area undershoot area maximum amplitude vdd vss volts(v) time(ns) maximum amplitude vddq vssq volts(v) time(ns) maximum amplitude overshoot area
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 41 rev. c 1 11/12 /2014 5.7 34ohm output driver dc electrical characteristics a functional representation of the output buffer is shown as below. output driver impedance ron is defined by the value ofthe external reference resistor rzq as follows: ron34 = rzq / 7 (nominal 34.4ohms +/ - 10% with nominal rzq=240ohms) the individual pull - up and pull - down resistors (ronpu and ronpd) are de fined as follows: ronpu = [vddq - vout] / | iout | ------------------- under the condition that ronpd is turned off (1) ronpd = vout / | iout | ------------------------------- under the condition that ronpu is turned off (2) figure 5.7 output driver : definition of voltages and currents 5.7.1 output driver dc electrical characteristics ddr3 (assuming 1.5v , rzq = 240ohms; entire operating temperature range; after proper zq calibration) ronnom resistor vout min nom max unit notes 34 ohms ron34pd voldc=0.2xvddq 0.6 1 1.1 rzq/7 1,2,3 vomdc=0.5xvddq 0.9 1 1.1 rzq/7 1,2,3 vohdc =0.8xvddq 0.9 1 1.4 rzq/7 1,2,3 ron34pu voldc=0.2xvddq 0.9 1 1.4 rzq/7 1,2,3 vomdc=0.5xvddq 0.9 1 1.1 rzq/7 1,2,3 vohdc=0.8xvddq 0.6 1 1.1 rzq/7 1,2,3 40 ohms ron40pd voldc=0.2xvddq 0.6 1 1.1 rzq/6 1,2,3 vomdc=0.5xvddq 0.9 1 1.1 rzq/6 1,2,3 vohdc =0.8xvddq 0.9 1 1.4 rzq/6 1,2,3 ron40pu voldc=0.2xvddq 0.9 1 1.4 rzq/6 1,2,3 vomdc=0.5xvddq 0.9 1 1.1 rzq/6 1,2,3 vohdc=0.8xvddq 0.6 1 1.1 rzq/6 1,2,3 mismatch between pull - up and pull - down, mmpupd vomdc= 0.5xvddq - 10 +10 % 1,2,4 vddq dq vssq to other circuitry ronpu ronpd i pu i pd output driver chip in drive mode iout vout
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 42 rev. c 1 11/12 /2014 ddr3l (assuming 1.35v , rzq = 240ohms; entire operating temperature range; after proper zq calibration) ronnom resistor vout min nom max unit notes 34 ohms ron34pd voldc=0.2xvddq 0.6 1 1.15 rzq/7 1,2,3 vomdc=0.5xvddq 0.9 1 1.15 rzq/7 1,2,3 vohdc =0.8xvddq 0.9 1 1.45 rzq/7 1,2,3 ron34pu voldc=0.2xvddq 0.9 1 1.45 rzq/7 1,2,3 vomdc=0.5xvddq 0.9 1 1.15 rzq/7 1,2,3 vohdc=0.8xvddq 0.6 1 1.15 rzq/7 1,2,3 40 ohms ron40pd voldc=0.2xvddq 0.6 1 1.15 rzq/6 1,2,3 vomdc=0.5xvddq 0.9 1 1.15 rzq/6 1,2,3 vohdc =0.8xvddq 0.9 1 1.45 rzq/6 1,2,3 ron40pu voldc=0.2xvddq 0.9 1 1.45 rzq/6 1,2,3 vomdc=0.5xvddq 0.9 1 1.1 5 rzq/6 1,2,3 vohdc=0.8xvddq 0.6 1 1.1 5 rzq/6 1,2,3 mismatch between pull - up and pull - down, mmpupd vomdc= 0.5xvddq - 10 +10 % 1,2,4 notes: 1. the tolerance limits are specified after calibration with stable voltage and temperature. for the behavior of the tolerance limits if tempe rature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 2. the tolerance limits ar e specified under the condition that vddq=vdd and that vssq=vss. 3. pull - down and pull - up output driver impedances are recommended to be calibrated at 0.5xvddq. other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 * vddq and 0.8 x vddq. 4. measurement definition for mismatch between pull - up and pull - down, mmpupd: measure ronpu and ronpd, both at 0.5 x vddq: mmpupd = [ronpu - ronpd] / ronnom x 100 5.7.2 output driver temperature and voltage sensitivity if temperature and/or voltage after calibration, the tolerance limits widen according to the following table below. delta t = t - t(@calibration); delta v = vddq - vddq(@calibration); vdd = vddq 5.7.2.1 output driver sensitivity definition items min. max. unit ronpu@vohdc 0.6 - drondth*ldelta tl - drondvh*ldelta vl 1.1 + drondth*ldelta tl - drondvh*ldelta vl rzq/7 ron@vomdc 0.9 - drondtm*ldelta tl - drondvm*ldelta vl 1.1 + drondtm*ldelta tl - drondvm*ldelta vl rzq/7 ronpd@voldc 0.6 - drondtl*ldelta tl - drondvl*ldelta vl 1.1 + drondtl*ldelta tl - drondvl*ldelta vl rzq/7 note: drondt and drondv are not subject to production test but are verified by design and characterization.
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 43 rev. c 1 11/12 /2014 5.7.2.2 output driver voltage and temperature sensitivity speed bin ddr3 - 800/1066/1333 ddr3 - 1600 /1866/2133 unit items min. max min. max drondtm 0 1.5 0 1.5 %/ c drondvm 0 0.15 0 0.13 %/mv drondtl 0 1.5 0 1.5 %/ c drondvl 0 0.15 0 0.13 %/mv drondth 0 1.5 0 1.5 %/ c drondvh 0 0.15 0 0.13 %/mv note: drondt and drondv are not subject to production test but are verified by design and characterization. 5.8 on - die termination (odt) levels and i - v characteristics 5.8.1 on - die termination (odt) levels and i - v characteristics on - die termination effective resistance rtt is defined by bits a9, a6, and a2 of the mr1 register. odt is applied to the dq, dm, dqs/dqs, and tdqs/tdqs (x8 devices only) pins. a functional representation of the on - die termination is shown in the following figure. the individual pull - up and pull - down resistors (rttpu and rttpd) are defined as follows: rttpu = [vddq - vout] / | iout | ------------------ under the condition that rttpd is turned off (3) rttpd = vout / | iout | ------------------------------ under the condition that rttpu is turned of f (4) figure 5.8.1 on - die termination : definition of voltages and currents 5.8.2 odt dc electrical characteristics the following table provides an overview of the odt dc electrical characteristics. the values for rtt60pd120, rtt60pu120, rtt120pd240, rtt120pu240, rtt40pd80, rtt40pu80, rtt30pd60, rtt30pu60, rtt20pd40, rtt20pu40 are not specification requi rements, but can be used as design guide lines: vddq dq vssq to other circuitry rttpu rttpd i pu i pd odt chip in termination mode iout vout iout = ipd - ipu
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 44 rev. c 1 11/12 /2014 odt dc electrical characteristics (assuming rzq = 240ohms +/ - 1% entire operating temperature range; after proper zq calibration) mr1 a9, a6, a2 rtt resistor vout min nom max (ddr3) max (ddr3l) unit notes 0,1,0 120 ? rtt120pd240 voldc = 0.2 x vddq 0.6 1 1.1 1.15 rzq 1,2,3,4 0.5 x vddq 0.9 1 1.1 1.15 rzq 1,2,3,4 vohdc = 0.8 x vddq 0.9 1 1.4 1.45 rzq 1,2,3,4 rtt120p u 240 voldc = 0.2 x vddq 0. 9 1 1.4 1.45 rzq 1,2,3,4 0.5 x vddq 0.9 1 1.1 1.15 rzq 1,2,3,4 vohdc = 0.8 x vddq 0. 6 1 1.1 1.15 rzq 1,2,3,4 rtt120 vil(ac) to vih(ac) 0.9 1 1.6 1.65 rzq/2 1,2,5 0,0,1 60 ? rtt 60pd120 voldc = 0.2 x vddq 0.6 1 1.1 1.15 rzq/2 1,2,3,4 0.5 x vddq 0.9 1 1.1 1.15 rzq/2 1,2,3,4 vohdc = 0.8 x vddq 0.9 1 1.4 1.45 rzq/2 1,2,3,4 rtt 60pu120 voldc = 0.2 x vddq 0.9 1 1.4 1.45 rzq/2 1,2,3,4 0.5 x vddq 0.9 1 1.1 1.15 rzq/2 1,2,3,4 vohdc = 0.8 x vddq 0. 6 1 1. 1 1.15 rzq/2 1,2,3,4 rtt60 vil(ac) to vih(ac) 0.9 1 1.6 1.65 rzq/4 1,2,5 0,1,1 40 ? rtt40pd80 voldc = 0.2 x vddq 0.6 1 1.1 1.15 rzq/3 1,2,3,4 0.5 x vddq 0.9 1 1.1 1.15 rzq/3 1,2,3,4 vohdc = 0.8 x vddq 0.9 1 1.4 1.45 rzq/3 1,2,3,4 rtt40pu80 voldc = 0.2 x vddq 0.9 1 1.4 1.45 rzq/3 1,2,3,4 0.5 x vddq 0.9 1 1.1 1.15 rzq/3 1,2,3,4 vohdc = 0.8 x vddq 0. 6 1 1.1 1.15 rzq/3 1,2,3,4 rtt40 vil(ac) to vih(ac) 0.9 1 1.6 1.65 rzq/6 1,2,5 1,0,1 30 ? rtt30pd60 voldc = 0.2 x vddq 0.6 1 1.1 1.15 rzq/4 1,2,3,4 0.5 x vddq 0.9 1 1.1 1.15 rzq/4 1,2,3,4 vohdc = 0.8 x vddq 0.9 1 1.4 1.45 rzq/4 1,2,3,4 rtt30pu60 voldc = 0.2 x vddq 0.9 1 1.4 1.45 rzq/4 1,2,3,4 0.5 x vddq 0.9 1 1.1 1.15 rzq/4 1,2,3,4 vohdc = 0.8 x vddq 0. 6 1 1.1 1.15 rzq/4 1,2,3,4 rtt30 vil(ac) to vih(ac) 0.9 1 1.6 1.65 rzq/8 1,2,5 1,0,0 20 ? rtt20pd40 voldc = 0.2 x vddq 0.6 1 1.1 1.15 rzq/6 1,2,3,4 0.5 x vddq 0.9 1 1.1 1.15 rzq/6 1,2,3,4 vohdc = 0.8 x vddq 0.9 1 1.4 1.45 rzq/6 1,2,3,4 rtt20pu40 voldc = 0.2 x vddq 0.9 1 1.4 1.45 rzq/6 1,2,3,4 0.5 x vddq 0.9 1 1.1 1.15 rzq/6 1,2,3,4 vohdc = 0.8 x vddq 0. 6 1 1.1 1.15 rzq/6 1,2,3,4 rtt20 vil(ac) to vih(ac) 0.9 1 1.6 1.65 rzq/12 1,2,5 deviation of vm w.r.t vddq/2, dvm - 5 - +5 +5 % 1,2,5 ,6 notes: 1. the tolerance limits are specified after calibration with stable voltage and temperature. for the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 2. the tolerance limits are specified under the condition that vddq = vdd and that vssq = vss. 3. pull - down and pull - up odt resistors are recommended to be calibrated at 0.5 x vddq. other calibration schemes may be used to achieve the linearity spec shown above. 4. not a specification requirement, but a design guide line. 5. measurement definition for rtt: apply vih(ac) to pin under test and measure current i(vih(ac)), then apply vil(ac) to pin under test and measure current i(vi l(ac)) respectively. rtt = [vih(ac) - vil(ac)] / [i(vih(ac)) - i(vil(ac))] 6. measurement definition for vm and dvm: measur e voltage (vm) at test pin (midpoint) with no load: delta v m = [2v m / vddq - 1] x 100
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 45 rev. c 1 11/12 /2014 5.8.3 odt temperature and voltage sensitivity if temperature and/or voltage after calibration, the tolerance limits widen according to the following table. delta t = t - t(@calibration); delta v = vddq - vddq(@calibration); vdd = vddq 5.8.3.1 odt sensitivity definition min max unit rtt 0.9 - drttdt*ldelta tl - drttdv*ldelta vl 1.6 + drttdt*ldelta tl + drttdv*ldelta vl rzq/2,4,6,8,12 5.8.3.2 odt voltage and temperature sensitivity min max unit drttdt 0 1.5 %/ c drttdv 0 0.15 %/mv note: these parameters may not be subject to production test. they are verified by design and characterization 5.9 odt timing definitions 5.9.1 test load for odt timings different than for timing measurements, the reference load for odt timings is defined in the following figure. figure 5.9.1 odt timing reference load 5.9.2 odt timing definitions definitions for t aon , t aonpd , t aof , t aofpd , and t adc are provided in the following table and subsequent figures. symbol begin point definition end point definition t aon rising edge of ck - ck defined by the end point of odtlon extrapolated point at vssq t aonpd rising edge of ck - ck with odt being first registered high extrapolated point at vssq t aof rising edge of ck - ck defined by the end point of odtloff end point: extrapolated point at v rtt_nom t aofpd rising edge of ck - ck with odt being first registered low end point: extrapolated point at v rtt_nom t adc rising edge of ck - ck defined by the end point of odtlcnw, odtlcwn4, or odtlcwn8 end point: extrapolated point at v rtt_wr and v rtt_nom respe ctively reference settings for odt timing measurements measured parameter rtt_nom setting rtt_wr setting vsw1[v] vsw2[v] t aon rzq/4 na 0.05 0.10 rzq/12 na 0.10 0.20 t aonpd rzq/4 na 0.05 0.10 rzq/12 na 0.10 0.20 t aofpd rzq/4 na 0.05 0.10 rzq/12 na 0.10 0.20 t adc ddr3 rzq/12 rzq/2 0.20 0.30 ddr3l rzq/12 r zq/ 2 0.20 0.25 ck,ck# dut dq, dm dqs, dqs# , tdqs, tdqs# 25ohm vtt=vssq timing reference point vddq vssq
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 46 rev. c 1 11/12 /2014 figure 5.9.2.1 definition of t aon figure 5.9.2. 2 definition of t aonpd begin point : rising edge of ck - ck# with odt being first register high end point : extrapolated point at vssq ck ck# vtt vsw2 dq,dm,dqs, dqs #,tdqs, tdqs# vssq t aonpd vsw1 tsw1 tsw2 begin point : rising edge of ck - ck# defined by the end of odtlon end point : extrapolated point at vssq ck ck# vtt vsw2 dq,dm,dqs, dqs#,tdqs, tdqs# vssq t aon vsw1 tsw1 tsw2
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 47 rev. c 1 11/12 /2014 figure 5.9.2. 3 definition of t aof figure 5.9.2. 4 definition of t aof pd begin point : rising edge of ck - ck# with defined by the end point of odtloff end point : extrapolated point at v rtt_nom ck ck# vtt vsw2 dq,dm,dqs, dqs#,tdqs, tdqs# vssq t aof vsw1 tsw1 tsw2 v rtt_nom begin point : rising edge of ck - ck# with odt being first registered low end point : extrapolated point at v rtt_nom ck ck# vtt vsw2 dq,dm,dqs, dqs#,tdqs, tdqs# vssq t aof pd vsw1 tsw1 tsw2 v rtt_nom
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 48 rev. c 1 11/12 /2014 figure 5.9.2. 5 definition of t a dc begin point : rising edge of ck - ck# defined by the end point of odtlcnw begin point : rising edge of ck - ck# defined by the end point of odtlcwn4 or odtlcwn8 t a dc t a dc end point : extrapolated point at v rtt_ wr end point : extrapolated point at v rtt_nom dq,dm,dqs, dqs#,tdqs, tdqs# ck ck# vtt vssq v rtt_nom tsw11 tsw21 tsw22 tsw12 vsw2 vsw1 v rtt_wr
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 49 rev. c 1 11/12 /2014 6. input / output capac itance symbol parameter ddr3/ ddr3l - 800 ddr3/ ddr3l - 1066 ddr3/ ddr3l - 1333 ddr3/ ddr 3l - 1600 ddr3/ ddr3l - 1 866 ddr3 - 2133 units notes min max min max min max min max min max min max c io input/output capacitance (dq, dm, dqs, dqs#,tdqs,td q s#) ddr3 1.4 3 1.4 2.7 1.4 2.5 1.4 2.3 1.4 2.2 1.4 2.1 pf 1,2,3 ddr3l 1.4 2.5 1.4 2.5 1.4 2.3 1.4 2.2 1.4 2.1 - - c ck input capacitance, ck and ck# 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 0.8 1.3 pf 2,3 c dck input capacitance delta, ck and ck# 0 0.15 0 0.15 0 0.15 0 0.15 0 0 .15 0 0.15 pf 2,3,4 c ddqs input/output capacitance delta, dqs and dqs# 0 0.15 0 0.15 0 0.15 0 0.15 0 0 .15 0 0.15 pf 2,3,5 c i input capacitance, ctrl, add, command input - only pins ddr3 0.75 1.4 0.75 1.35 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 pf 2,3,7, 8 ddr3l 0.75 1.3 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 - - c di_ctrl input capacitance delta, all ctrl input - only pins - 0.5 0.3 - 0.5 0.3 - 0.4 0.2 - 0.4 0.2 - 0.4 0.2 - 0.4 0.2 pf 2,3,7, 8 c di_add_c md input capacitance delta, all add/cmd input - only pins - 0.5 0.5 - 0.5 0.5 - 0.4 0.4 - 0.4 0.4 - 0.4 0.4 - 0.4 0.4 pf 2,3,9, 10 c dio input/output capacitance delta, dq, dm, dqs, dqs# tdqs,tdqs# - 0.5 0.3 - 0.5 0.3 - 0.5 0.3 - 0.5 0.3 - 0.5 0.3 - 0.5 0.3 pf 2,3,11 c zq input/output capacitance of zq pin - 3 - 3 - 3 - 3 - 3 - 3 pf 2,3,12 notes: 1. although the dm, tdqs and tdqs# pins have different functions, the loading matches dq and dqs 2. this parameter is not subject to production test. it is verified by design and characterization. vdd=vddq=1.5v, vbias=vdd/2 a nd on - die termination off. 3. this parameter applies to monolithic devices only; stacked/dua l - die devices are not covered here 4. absolute value of c ck - c ck # 5. absolute value of c io (dqs) - c io (dqs#) 6. c i applies to odt, cs#, cke, a0 - a13, ba0 - ba2, ras#,cas#,we#. 7. c di_ctrl applies to odt, cs# and cke 8. c di_ctrl =c i (ctrl) - 0.5*(c i (ck)+c i (ck#)) 9. c di_add_cmd applies to a0 - a13, ba0 - ba2, ras#, cas# and we# 10. c di_add_cmd =c i (add_cmd) - 0.5*(c i (ck)+c i (ck#)) 11. c dio =c io (dq,dm) - 0.5*(c io (dqs)+c io (dqs#)) 12. maximum external load capacitance on zq pin: 5 pf.
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 50 rev. c 1 11/12 /2014 7. i dd specifications an d measurement condit ions idd specificati ons (x8), 1.5 operation voltage symbol parameter/condition ddr3 - 1066 ddr3 - 1333 ddr3 - 1600 ddr3 - 1866 ddr3 - 2133 unit max. max. max. max. max. idd0 operating current 0 - > one bank activate - > precharge 55 60 65 70 75 ma idd1 operating current 1 - > one bank activate - > read - > precharge 70 75 80 90 100 ma idd2p0 precharge power - down current slow exit - mr0 bit a12 = 0 12 12 12 14 14 ma idd2p1 precharge power - down current fast exit - mr0 bit a12 = 1 20 20 20 24 29 ma idd2pq precharge quiet standby current 28 29 30 40 42 ma idd2n precharge standby current 30 33 35 44 46 ma idd3p active power - down current always fast exit 30 30 33 50 52 ma idd3n active standby current 50 53 55 60 65 ma idd4r operating current burst read 120 125 140 175 200 ma idd4w operating current burst write 125 130 150 180 210 ma idd5b burst refresh current 160 160 165 170 175 ma idd6 self - refresh current normal temperature range (0 - 85c) 12 12 12 14 14 ma idd6et self - refresh current: extended temperature range 14 14 14 16 16 ma idd7 all bank interleave read current 200 215 240 270 295 ma note : 1066 is for reference only
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 51 rev. c 1 11/12 /2014 idd specifications (x16), 1.5 operation voltage symbol parameter/condition ddr3 - 1066 ddr3 - 1333 ddr3 - 1600 ddr3 - 1866 ddr3 - 2133 unit max. max. max. max. max. idd0 operating current 0 - > one bank activate - > precharge 65 70 70 74 81 ma idd1 operating current 1 - > one bank activate - > read - > precharge 90 95 100 110 120 ma idd2p0 precharge power - down current slow exit - mr0 bit a12 = 0 12 12 12 14 14 ma idd2p1 precharge power - down current fast exit - mr0 bit a12 = 1 20 20 20 24 29 ma idd2pq precharge quiet standby current 30 30 30 40 42 ma idd2n precharge standby current 30 33 35 44 46 ma idd3p active power - down current always fast exit 27 30 33 50 52 ma idd3n active standby current 50 50 55 60 65 ma idd4r operating current burst read 160 170 180 214 237 ma idd4w operating current burst write 160 180 200 233 252 ma idd5b burst refresh current 155 160 165 170 175 ma idd6 self - refresh current normal temperature range (0 - 85c) 12 12 12 14 14 ma idd6et self - refresh current: extended temperature range 14 14 14 16 16 ma idd7 all bank interleave read current 240 255 280 310 320 ma note : 1066 is for reference only
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 52 rev. c 1 11/12 /2014 idd specifications (x8), 1.35 operation voltage symbol parameter/condition ddr3 l - 1066 ddr3 l - 1333 ddr3 l - 1600 ddr3 l - 1 866 unit max. max. max. max. idd0 operating current 0 - > one bank activate - > precharge 55 55 65 67 ma idd1 operating current 1 - > one bank activate - > read - > precharge 68 70 78 85 ma idd2p0 precharge power - down current slow exit - mr0 bit a12 = 0 11 11 11 13 ma idd2p1 precharge power - down current fast exit - mr0 bit a12 = 1 17 18 18 20 ma idd2pq precharge quiet standby current 26 28 30 35 ma idd2n precharge standby current 30 32 33 38 ma idd3p active power - down current always fast exit 30 30 34 40 ma idd3n active standby current 43 46 50 55 ma idd4r operating current burst read 115 120 130 170 ma idd4w operating current burst write 120 125 140 170 ma idd5b burst refresh current 153 156 160 165 ma idd6 self - refresh current normal temperature range (0 - 85c) 11 11 11 13 ma idd6et self - refresh current: extended temperature range 13 13 13 15 ma idd7 all bank interleave read current 195 205 220 255 ma note: 1066 is for reference only
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 53 rev. c 1 11/12 /2014 idd specifications (x16), 1.35 operation voltage symbol parameter/condition ddr3 l - 1066 ddr3 l - 1333 ddr3 l - 1600 ddr3 l - 1 866 unit max. max. max. max. idd0 operating current 0 - > one bank activate - > precharge 60 65 65 67 ma idd1 operating current 1 - > one bank activate - > read - > precharge 83 88 88 100 ma idd2p0 precharge power - down current slow exit - mr0 bit a12 = 0 11 11 11 13 ma idd2p1 precharge power - down current fast exit - mr0 bit a12 = 1 17 18 18 20 ma idd2pq precharge quiet standby current 26 28 30 35 ma idd2n precharge standby current 30 32 33 38 ma idd3p active power - down current always fast exit 30 30 34 40 ma idd3n active standby current 43 46 50 55 ma idd4r operating current burst read 150 158 166 194 ma idd4w operating current burst write 155 170 180 210 ma idd5b burst refresh current 153 156 160 165 ma idd6 self - refresh current normal temperature range (0 - 85c) 11 11 11 13 ma idd6et self - refresh current: extended temperature range 13 13 13 15 ma idd7 all bank interleave read current 230 245 265 293 ma note: 1066 is for reference only
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 54 rev. c 1 11/12 /2014 8. electrical character istics and ac timing for ddr3 - 800 to ddr3 - 1600 8.1 clock specification the jitter specified is a random jitter meeting a gaussian distribution. input clocks violating the min/max values may result in malfunction of the ddr 3 sdram device. 8.1.1 definition for tck(avg) tck(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to rising edge. w here n=200 8.1.2 definition for tck(abs) tck(abs) is defind as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tck(abs) is not subject to production test. 8.1.3 definition for tch(avg) and tcl(avg) tch(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses: w here n=200 tcl(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses: w here n=200 8.1.4 definition for note for tjit(per), tjit(per, ick) tjit(per) is defined as the largest deviation of any single tck from tck(avg). tjit(per) = min/max of {tcki - tck(avg) where i=1 to 200} tjit(per) defines the single period jitter when the dll is already locked. tjit(per,lck) uses the same definition for single period jitter, durin g the dll locking period only. tjit(per) and tjit(per,lck) are not subject to production test. tck (avg) = ( tckj ) / n tch (avg) = ( tchj ) / (n x tck(avg) tcl (avg) = ( tclj ) / (n x tck(avg)
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 55 rev. c 1 11/12 /2014 8.1.5 definition for tjit(cc), tjit(cc, ick) tjit(cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tjit(cc) = m ax of {tcki+1 - tcki} tjit(cc) defines the cycle to cycle jitter when the dll is already locked. tjit(cc,lck) uses the same definition for cycle to cycle jitter, during the dll locking period only. tjit(cc) and tjit(cc,lck) are not subject to production test . 8.1.6 definition for terr(nper) terr is defined as the cumulative error across n multiple consecutive cycles from tck(avg). terr is not subject to production test. 8.2 refresh parameters refresh parameters (1) parameter symbol units all bank refresh to active/refresh cmd time trfc 1 1 0 ns average periodic refresh interval trefi - 40c < tcase < 85c 7.8 s 85c < tcase < 105c 3.9 s notes: 1. the permissible tcase operating temperature is specified by temperature grade. the m aximum tcase is 95 c unless a2 grade, for which the maximum is 105 ? c. refer to 3.2 component operating temperature range. 8.3 speed bins and cl, trcd, trp, trc and tras for corresponding bin ddr3 - 1066mt/s speed bin ddr3/ddr3l - 1066 unit cl - nrcd - nrp 7 - 7 - 7 ( - 187f) parameter symbol min max internal read command to first data taa 13.125 20.000 ns act to internal read or write delay time trcd 13.125 - ns pre command period trp 13.125 - ns act to act or ref command period trc 50.625 - ns act to pre command period tras 37.500 9*trefi ns cl=5 cwl =5 tck(avg) 3.000 3.300 ns cwl=6 tck(avg) reserved ns cl=6 cwl =5 tck(avg) 2.500 3.300 ns cwl=6 tck(avg) reserved ns cl=7 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) 1.875 <2.5 ns cl=8 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) 1.875 <2.5 ns supported cl settings 5,6,7,8 nck supported cwl settings 5,6 nck
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 56 rev. c 1 11/12 /2014 ddr3 - 1333mt/s speed bin ddr3/ddr3l - 1 333 unit cl - nrcd - nrp 9 - 9 - 9 ( - 15h) parameter symbol min max internal read command to first data taa 1 3 . 5 20 ns act to internal read or write delay trcd 1 3 . 5 - ns pre command period trp 1 3 . 5 - ns act to act or ref period trc 4 9 . 5 - ns act to pre command period tras 3 6.0 9*trefi ns cl=5 cwl =5 tck(avg) 3.0 3.3 ns cwl=6 tck(avg) reserved ns cwl=7 tck(avg) reserved ns cl=6 cwl =5 tck(avg) 2.5 3.3 ns cwl=6 tck(avg) reserved ns cwl=7 tck(avg) reserved ns cl=7 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) 1.875 <2.5 ns cwl=7 tck(avg) reserved ns cl=8 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) 1.875 <2.5 ns cwl=7 tck(avg) reserved ns cl=9 cwl=5 tck(avg) reserved ns cwl= 6 tck(avg) reserved ns cwl= 7 tck(avg) 1.5 <1.875 ns cl=10 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) reserved ns cwl=7 tck(avg) 1.5 <1.875 ns supported cl settings 5,6, 7, 8,9,10 nck supported cwl settings 5,6, 7 nck note : *: - 15h is compatible with slower speed options ddr3 - 1333mt/s speed bin ddr3/ddr3l - 1 333 unit cl - nrcd - nrp 8 - 8 - 8 ( - 15 g ) parameter symbol min max internal read command to first data taa 12.0 20 ns act to internal read or write delay trcd 12.0 - ns pre command period trp 12.0 - ns act to act or ref period trc 48.0 - ns act to pre command period tras 3 6.0 9*trefi ns cl=5 cwl =5 tck(avg) 2.5 3.3 ns cwl=6 tck(avg) reserved ns cwl=7 tck(avg) reserved ns cl=6 cwl =5 tck(avg) 2.5 3.3 ns cwl=6 tck(avg) reserved ns cwl=7 tck(avg) reserved ns
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 57 rev. c 1 11/12 /2014 cl=7 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) 1.875 <2.5 ns cwl=7 tck(avg) reserved ns cl=8 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) 1.875 <2.5 ns cwl=7 tck(avg) 1. 5 1.875 ns cl=9 cwl=5 tck(avg) reserved ns cwl= 6 tck(avg) reserved ns cwl= 7 tck(avg) 1.5 <1.875 ns cl=10 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) reserved ns cwl=7 tck(avg) 1.5 <1.875 ns supported cl settings 5,6, 7, 8,9,10 nck supported cwl settings 5,6, 7 nck note : *: - 15 g is compatible with slower speed options. ddr3 - 1600mt/s speed bin ddr3/ddr3l - 1600 unit cl - nrcd - nrp 10 - 10 - 10 ( - 125 j ) parameter symbol min max internal read command to first data taa 12.5 20 ns act to internal read or write delay trcd 12.5 - ns pre command period trp 12.5 - ns act to act or ref period trc 47.5 - ns act to pre command period tras 35 9*trefi ns cl=5 cwl =5 tck(avg) 2.5 3.3 ns cwl=6 tck(avg) reserved ns cwl=7 tck(avg) reserved ns cwl=8 tck(avg) reserved ns cl=6 cwl =5 tck(avg) 2.5 3.3 ns cwl=6 tck(avg) reserved ns cwl=7 tck(avg) reserved ns cwl=8 tck(avg) reserved ns cl=7 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) 1.875 <2.5 ns cwl=7 tck(avg) reserved ns cwl=8 tck(avg) reserved ns cl=8 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) 1.875 <2.5 ns cwl=7 tck(avg) reserved ns cwl=8 tck(avg) reserved ns cl=9 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) reserved ns cwl=7 tck(avg) 1. 5 <1.875 ns cwl=8 tck(avg) reserved ns cl=10 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) reserved ns cwl=7 tck(avg) 1.5 <1.875 ns cwl =8 tck(avg) 1.25 <1.5 ns
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 58 rev. c 1 11/12 /2014 cl=11 cwl =5 tck(avg) reserved ns cwl= 6 tck(avg) reserved ns cwl= 7 tck(avg) reserved ns cwl = 8 tck(avg) 1. 25 <1. 5 ns supported cl settings 5,6,7,8,9,10,11 nck supported cwl settings 5,6,7,8 nck note : *: - 125j is backward compatible with slower spee d options, except - 15g when vdd, vddq = 1.35v. ddr3 - 1866mt/s speed bin ddr3/ddr3l - 1866 unit cl - nrcd - nrp 13 - 13 - 13 ( - 107 m ) parameter symbol min max internal read command to first data taa 13.91 20 ns act to internal read or write delay trcd 13.91 - ns pre command period trp 13.91 - ns act to act or ref period trc 47.91 - ns act to pre command period tras 34 9*trefi ns cl=5 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) reserved ns cwl=7 tck(avg) reserved ns cwl=8 ,9 tck(avg) reserved ns cl=6 cwl =5 tck(avg) 2.5 3.3 ns cwl=6 tck(avg) reserved ns cwl=7 tck(avg) reserved ns cwl=8 ,9 tck(avg) reserved ns cl=7 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) 1.875 <2.5 ns cwl=7 tck(avg) reserved ns cwl=8 ,9 tck(avg) reserved ns cl=8 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) 1.875 <2.5 ns cwl=7 tck(avg) reserved ns cwl=8 ,9 tck(avg) reserved ns cl=9 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) reserved ns cwl=7 tck(avg) 1.5 <1.875 ns cwl=8 ,9 tck(avg) reserved ns cl=10 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) reserved ns cwl=7 tck(avg) 1.5 < 1.875 ns cwl =8 ,9 tck(avg) reserved ns cl= 11 cwl =5 ,6 tck(avg) reserved ns cwl= 7 tck(avg) reserved ns cwl= 8 tck(avg) 1. 2 5 <1. 5 ns cwl =9 tck(avg) reserved ns
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 59 rev. c 1 11/12 /2014 cl=12 cwl=5,6, 7,8,9 tck(avg) reserved ns cl=13 cwl=5,6, 7,8 tck(avg) reserved ns cwl =9 tck(avg) 1.07 <1.25 ns supported cl settings 5,6,7,8,9,10,11,12,1 3 nck supported cwl settings 5,6,7,8,9 nck note : - 107m is bac kward compatible with slower spe e d options, except - 15g when vdd, vddq = 1.35v . ddr3 - 2133 mt/s speed bin ddr3 - 2133 unit cl - nrcd - nrp 14 - 14 - 14 ( - 093n ) parameter symbol min max internal read command to first data taa 13.09 20 ns act to internal read or write delay trcd 13.09 - ns pre command period trp 13.09 - ns act to act or ref period trc 46.09 - ns act to pre command period tras 33 9*trefi ns cl=5 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) reserved ns cwl=7 tck(avg) reserved ns cwl=8 ,9,10 tck(avg) reserved ns cl=6 cwl =5 tck(avg) 2.5 3.3 ns cwl=6 tck(avg) reserved ns cwl=7 tck(avg) reserved ns cwl=8 ,9,10 tck(avg) reserved ns cl=7 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) 1.875 <2.5 ns cwl=7 tck(avg) reserved ns cwl=8 ,9,10 tck(avg) reserved ns cl=8 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) 1.875 <2.5 ns cwl=7 tck(avg) reserved ns cwl=8 ,9,10 tck(avg) reserved ns cl=9 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) reserved ns cwl=7 tck(avg) 1.5 <1.875 ns cwl=8 ,9,10 tck(avg) reserved ns cl=10 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) reserved ns cwl=7 tck(avg) 1.5 <1.875 ns cwl =8 ,9,10 tck(avg) reserved ns cl= 11 cwl =5 ,6 tck(avg) reserved ns cwl= 7 tck(avg) reserved ns cwl= 8 tck(avg) 1. 2 5 <1. 5 ns cwl =9,10 tck(avg) reserved ns
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 60 rev. c 1 11/12 /2014 cl=12 cwl=5,6,7,8,9 tck(avg) reserved ns cl=13 cwl=5,6,7,8 tck(avg) reserved ns cwl =9 tck(avg) 1.07 <1.25 ns cwl =10 tck(avg) reserved ns cl=1 4 cwl=5,6,7,8 ,9 tck(avg) reserved ns cwl =10 tck(avg) 0.938 <1.07 ns supported cl settings 5,6,7,8,9,10,11,12,1 3,14 nck supported cwl settings 5,6,7,8,9 ,10 nck note : - 093n is backward compatible with slower speed options, except - 15g when vdd, vddq = 1.35v 9. electrical charac teristics & ac timin g 9.1 timing parameter by speed bin (ddr3 - 800, ddr3 - 1066) parameter symbol ddr3/ddr3l - 800 ddr3/ddr3l - 1066 units notes min. max. min. max. clock timing minimum clock cycle time (dll off mode) tck(dll_off) 8 - 8 - ns 6 average clock period tck(avg) refer to standard speed bins ps average high pulse width tch(avg) 0.47 0.53 0.47 0.53 tck(avg) average low pulse width tcl(avg) 0.47 0.53 0.47 0.53 tck(avg) absolute clock period tck(abs) min.: tck(avg)min + tjit(per)min ps max.: tck(avg)max + tjit(per)max absolute clock high pulse width tch(abs) 0.43 - 0.43 - tck(avg) 25 absolute clock low pulse width tcl(abs) 0.43 - 0.43 - tck(avg) 26 clock period jitter jit(per) - 100 100 - 90 90 ps clock period jitter during dll locking period jit(per, lck) - 90 90 - 80 80 ps cycle to cycle period jitter tjit(cc) 200 200 180 180 ps cycle to cycle period jitter during dll locking period jit(cc, lck) 180 180 160 160 ps duty cycle jitter tjit(duty) - - - - ps cumulative error across 2 cycles terr(2per) - 147 147 - 132 132 ps cumulative error across 3 cycles terr(3per) - 175 175 - 157 157 ps cumulative error across 4 cycles terr(4per) - 194 194 - 175 175 ps cumulative error across 5 cycles terr(5per) - 209 209 - 188 188 ps cumulative error across 6 cycles terr(6per) - 222 222 - 200 200 ps cumulative error across 7 cycles terr(7per) - 232 232 - 209 209 ps cumulative error across 8 cycles terr(8per) - 241 241 - 217 217 ps cumulative error across 9 cycles terr(9per) - 249 249 - 224 224 ps cumulative error across 10 cycles terr(10per) - 257 257 - 231 231 ps cumulative error across 11 cycles terr(11per) - 263 263 - 237 237 ps
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 61 rev. c 1 11/12 /2014 parameter symbol ddr3/ddr3l - 800 ddr3/ddr3l - 1066 units notes min. max. min. max. cumulative error across 12 cycles terr(12per) - 269 269 - 242 242 ps cumulative error across n = 13, 14 . . . 49, 50 cycles terr(nper) terr(nper)min = (1 + 0.68ln(n)) * tjit(per)min ps 24 terr(nper)max = (1 + 0.68ln(n)) * tjit(per)max data timing dqs, dqs# to dq skew, per group, per access tdqsq - 200 - 150 ps 13 dq output hold time from dqs, dqs# tqh 0.38 - 0.38 - tck(avg) 13,g dq low - impedance time from ck, ck# tlz(dq) - 800 400 - 600 300 ps 13,14,f dq high impedance time from ck, ck# thz(dq) - 400 - 300 ps 13,14,f data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels tds(base) ac175 or ac160 see table for data setup and hold ps d,17 data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels tds(base) ac150 or ac135 ps d,17 data hold time from dqs, dqs# referenced to vih(dc) / vil(dc) levels tdh(base) dc100 or dc90 ps d,17 dq and dm input pulse width for each input tdipw 600 - 490 - ps 28 data strobe timing dqs,dqs# differential read preamble trpre 0.9 note 19 0.9 note 19 tck(avg) 13,19,g dqs, dqs# differential read postamble trpst 0.3 note 11 0.3 note 11 tck(avg) 11,13,g dqs, dqs# differential output high time tqsh 0.38 - 0.38 - tck(avg) 13,g dqs, dqs# differential output low time tqsl 0.38 - 0.38 - tck(avg) 13,g dqs, dqs# differential write preamble twpre 0.9 - 0.9 - tck(avg) dqs, dqs# differential write postamble twpst 0.3 - 0.3 - tck(avg) dqs, dqs# rising edge output access time from rising ck, ck# tdqsck - 400 400 - 300 300 ps 13,f dqs and dqs# low - impedance time (referenced from rl - 1) tlz(dqs) - 800 400 - 600 300 ps 13,14,f dqs and dqs# high - impedance time (referenced from rl + bl/2) thz(dqs) - 400 - 300 ps 13,14,f dqs, dqs# differential input low pulse width tdqsl 0.45 0.55 0.45 0.55 tck(avg) 29,31 dqs, dqs# differential input high pulse width tdqsh 0.45 0.55 0.45 0.55 tck(avg) 30,31 dqs, dqs# rising edge to ck, ck# rising edge tdqss - 0.25 0.25 - 0.25 0.25 tck(avg) c dqs, dqs# falling edge setup time to ck, ck# rising edge tdss 0.2 - 0.2 - tck(avg) c,32 dqs, dqs# falling edge hold time from ck, ck# rising edge tdsh 0.2 - 0.2 - tck(avg) c,32 command and address timing dll locking time tdllk 512 - 512 - nck internal read command to precharge command delay trtp trtpmin.: max(4nck, 7.5ns) e trtpmax.: - delay from start of internal write transaction to internal read command twtr twtrmin.: max(4nck, 7.5ns) e,18 twtrmax.: write recovery time twr 15 - 15 - ns e,18 mode register set command cycle time tmrd 4 - 4 - nck mode register set command update delay tmod tmodmin.: max(12nck, 15ns) tmodmax.: act to internal read or write delay time trcd standard speed bins e pre command period trp standard speed bins e act to act or ref command period trc standard speed bins e cas# to cas# command delay tccd 4 - 4 - nck
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 62 rev. c 1 11/12 /2014 parameter symbol ddr3/ddr3l - 800 ddr3/ddr3l - 1066 units notes min. max. min. max. auto precharge write recovery + precharge time tdal(min) wr + roundup(trp / tck(avg)) nck multi - purpose register recovery time tmprr 1 - 1 - nck 22 active to precharge command period tras standard speed bins e active to active command period for 1kb page size trrd max(4nck, 10ns) - max(4nck, 7.5ns) - e active to active command period for 2kb page size trrd trrdmin.: max(4nck, 10ns) e trrdmax.: four activate window for 1kb page size tfaw 40 - 37.5 - ns e four activate window for 2kb page size tfaw 50 - 50 - ns e command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) ac175 or ac160 see table for a dd /cmd setup and hold ps b,16 command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) ac150 or ac1 35 ps b,16,27 command and address hold time from ck, ck# referenced to vih(dc) / vil(dc) levels tih (base) dc100 or dc90 ps b,16 control and address input pulse width for each input tipw 900 - 780 - ps 28 calibration timing power - up and reset calibration time tzqinit m ax (512 nck, 640ns) - m ax (512 nck, 640ns) - normal operation full calibration time tzqoper m ax ( 256 nck, 320 ns) - m ax ( 256 nck, 320 ns) - normal operation short calibration time tzqcs m ax ( 64 nck, 8 0ns) - m ax ( 64 nck, 8 0ns) - 23 reset timing exit reset from cke high to a valid command txpr txprmin.: max(5nck, trfc(min) + 10ns) txprmax.: - self refresh timings exit self refresh to commands not requiring a locked dll txs txsmin.: max(5nck, trfc(min) + 10ns) txsmax.: - exit self refresh to commands requiring a locked dll txsdll txsdllmin.: tdllk(min) nck 2 txsdllmax.: - minimum cke low width for self refresh entry to exit timing tckesr tckesrmin.: tcke(min) + 1 nck tckesrmax.: - valid clock requirement after self refresh entry (sre) or power - down entry (pde) tcksre tcksremin.: max(5 nck, 10 ns) tcksremax.: - valid clock requirement before self refresh exit (srx) or power - down exit (pdx) or reset exit tcksrx tcksrxmin.: max(5 nck, 10 ns) tcksrxmax.: - power down timings exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll txp txpmin.: max(3nck, 7.5ns) txpmax.: - exit precharge power down with dll frozen to commands requiring a locked dll txpdll txpdllmin.: max(10nck, 24ns) txpdllmax.: - cke minimum pulse width tcke tckemin.: max(3nck 7.5ns) tckemin.: max(3nck 5.625ns) tckemax.: - tckemax.: - command pass disable delay tcpded tcpdedmin.: 1 nck tcpdedmax.: - power down entry to exit timing tpd tpdmin.: tcke(min) 15 tpdmax.: 9*trefi
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 63 rev. c 1 11/12 /2014 parameter symbol ddr3/ddr3l - 800 ddr3/ddr3l - 1066 units notes min. max. min. max. timing of act command to power down entry tactpden tactpdenmin.: 1 nck 20 tactpdenmax.: - timing of pre or prea command to power down entry tprpden tprpdenmin.: 1 nck 20 tprpdenmax.: - parameter symbol ddr3 - 800 ddr3 - 1066 units notes min. max. min. max. timing of rd/rda command to power down entry trdpden trdpdenmin.: rl+4+1 nck trdpdenmax.: - timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) twrpden twrpdenmin.: wl + 4 + (twr / tck(avg)) nck 9 twrpdenmax.: - timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) twrapden twrapdenmin.: wl+4+wr+1 nck 10 twrapdenmax.: - timing of wr command to power down entry (bc4mrs) twrpden twrpdenmin.: wl + 2 + (twr / tck(avg)) nck 9 twrpdenmax.: - timing of wra command to power down entry (bc4mrs) twrapden twrapdenmin.: wl + 2 +wr + 1 nck 10 twrapdenmax.: - timing of ref command to power down entry trefpden trefpdenmin.: 1 nck 20,21 trefpdenmax.: - timing of mrs command to power down entry tmrspden tmrspdenmin.: tmod(min) tmrspdenmax.: - odt timings odt high time without write command or with write command and bc4 odth4 odth4min.: 4 nck odth4max.: - odt high time with write command and bl8 odth8 odth8min.: 6 nck odth8max.: - asynchronous rtt turn - on delay (power - down with dll frozen) taonpd 2 8.5 2 8.5 ns asynchronous rtt turn - off delay (power - down with dll frozen) taofpd 2 8.5 2 8.5 ns rtt turn - on taon - 400 400 - 300 300 ps 7,f rtt_nom and rtt_wr turn - off time from odtloff reference taof 0.3 0.7 0.3 0.7 tck(avg) 8,f rtt dynamic change skew tadc 0.3 0.7 0.3 0.7 tck(avg) f write leveling timings first dqs/dqs# rising edge after write leveling mode is programmed twlmrd 40 - 40 - nck 3 dqs/dqs# delay after write leveling mode is programmed twldqsen 25 - 25 - nck 3 write leveling setup time from rising ck, ck# crossing to rising dqs, dqs# crossing twls 325 - 245 - ps write leveling hold time from rising dqs, dqs# crossing to rising ck, ck# crossing twlh 325 - 245 - ps write leveling output delay twlo 0 9 0 9 ns write leveling output error twloe 0 2 0 2 ns
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 64 rev. c 1 11/12 /2014 9.2 timing parameter by speed bin (ddr3 - 1333, ddr3 - 1600) parameter symbol ddr3/ddr3l - 1333 ddr3/ddr3l - 1600 units notes min. max. min. max. clock timing minimum clock cycle time (dll off mode) tck(dll_off) 8 - 8 - ns 6 average clock period tck(avg) refer to standard speed bins ps average high pulse width tch(avg) 0.47 0.53 0.47 0.53 tck(avg) average low pulse width tcl(avg) 0.47 0.53 0.47 0.53 tck(avg) absolute clock period tck(abs) min.: tck(avg)min + tjit(per)min ps max.: tck(avg)max + tjit(per)max absolute clock high pulse width tch(abs) 0.43 - 0.43 - tck(avg) 25 absolute clock low pulse width tcl(abs) 0.43 - 0.43 - tck(avg) 26 clock period jitter jit(per) - 80 80 - 70 70 ps clock period jitter during dll locking period jit(per, lck) - 70 70 - 60 60 ps cycle to cycle period jitter tjit(cc) 160 160 140 140 ps cycle to cycle period jitter during dll locking period jit(cc, lck) 140 140 120 120 ps duty cycle jitter tjit(duty) - - - - ps cumulative error across 2 cycles terr(2per) - 118 118 - 103 103 ps cumulative error across 3 cycles terr(3per) - 140 140 - 122 122 ps cumulative error across 4 cycles terr(4per) - 155 155 - 136 136 ps cumulative error across 5 cycles terr(5per) - 168 168 - 147 147 ps cumulative error across 6 cycles terr(6per) - 177 177 - 155 155 ps cumulative error across 7 cycles terr(7per) - 186 186 - 163 163 ps cumulative error across 8 cycles terr(8per) - 193 193 - 169 169 ps cumulative error across 9 cycles terr(9per) - 200 200 - 175 175 ps cumulative error across 10 cycles terr(10per) - 205 205 - 180 180 ps cumulative error across 11 cycles terr(11per) - 210 210 - 184 184 ps cumulative error across 12 cycles terr(12per) - 215 215 - 188 188 ps cumulative error across n = 13, 14 . . . 49, 50 cycles terr(nper) terr(nper)min = (1 + 0.68ln(n)) * tjit(per)min ps 24 terr(nper)max = (1 + 0.68ln(n)) * tjit(per)max data timing dqs, dqs# to dq skew, per group, per access tdqsq - 125 - 100 ps 13 dq output hold time from dqs, dqs# tqh 0.38 - 0.38 - tck(avg) 13,g dq low - impedance time from ck, ck# tlz(dq) - 500 250 - 450 225 ps 13,14,f dq high impedance time from ck, ck# thz(dq) - 250 - 225 ps 13,14,f data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels tds(base) ac1 50 see table for data setup and hold ps d,17 data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels tds(base) ac1 35 ps d,17 data hold time from dqs, dqs# referenced to vih(dc) / vil(dc) levels tdh(base) dc100 or dc90 ps d,17 dq and dm input pulse width for each input tdipw 400 - 360 - ps 28 data strobe timing dqs,dqs# differential read preamble trpre 0.9 note 19 0.9 note 19 tck(avg) 13,19,g dqs, dqs# differential read postamble trpst 0.3 note 11 0.3 note 11 tck(avg) 11,13,g dqs, dqs# differential output high time tqsh 0.4 - 0.4 - tck(avg) 13,g dqs, dqs# differential output low time tqsl 0.4 - 0.4 - tck(avg) 13,g dqs, dqs# differential write preamble twpre 0.9 - 0.9 - tck(avg) dqs, dqs# differential write postamble twpst 0.3 - 0.3 - tck(avg) dqs, dqs# rising edge output access time from rising ck, ck# tdqsck - 255 255 - 225 225 ps 13,f
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 65 rev. c 1 11/12 /2014 parameter symbol ddr3/ddr3l - 1333 ddr3/ddr3l - 16 00 units notes min. max. min. max. dqs and dqs# low - impedance time (referenced from rl - 1) tlz(dqs) - 500 250 - 450 225 ps 13,14,f dqs and dqs# high - impedance time (referenced from rl + bl/2) thz(dqs) - 250 - 225 ps 13,14,f dqs, dqs# differential input low pulse width tdqsl 0.45 0.55 0.45 0.55 tck(avg) 29,31 dqs, dqs# differential input high pulse width tdqsh 0.45 0.55 0.45 0.55 tck(avg) 30,31 dqs, dqs# rising edge to ck, ck# rising edge tdqss - 0.25 0.25 - 0.27 0.27 tck(avg) c dqs, dqs# falling edge setup time to ck, ck# rising edge tdss 0.2 - 0.18 - tck(avg) c,32 dqs, dqs# falling edge hold time from ck, ck# rising edge tdsh 0.2 - 0.18 - tck(avg) c,32 command and address timing dll locking time tdllk 512 - 512 - nck internal read command to precharge command delay trtp trtpmin.: max(4nck, 7.5ns) trtpmax.: - delay from start of internal write transaction to internal read command twtr twtrmin.: max(4nck, 7.5ns) twtrmax.: write recovery time twr 15 - 15 - ns e,18 mode register set command cycle time tmrd 4 - 4 - nck mode register set command update delay tmod tmodmin.: max(12nck, 15ns) tmodmax.: act to internal read or write delay time trcd standard speed bins pre command period trp standard speed bins act to act or ref command period trc standard speed bins cas# to cas# command delay tccd 4 - 4 - nck auto precharge write recovery + precharge time tdal(min) wr + roundup(trp / tck(avg)) nck multi - purpose register recovery time tmprr 1 - 1 - nck 22 active to precharge command period tras standard speed bins active to active command period for 1kb page size trrd max(4nck, 6ns) - max(4nck, 6ns) - e active to active command period for 2kb page size trrd trrdmin.: max(4nck, 7.5ns) trrdmax.: four activate window for 1kb page size tfaw 30 - 30 - ns e four activate window for 2kb page size tfaw 45 - 40 - ns e command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) ac175 or ac160 see table for add/cmd setup and hold ps b,16 command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) ac150 or ac1 35 ps b,16,27 command and address hold time from ck, ck# referenced to vih(dc) / vil(dc) levels tih(base) dc100 or dc90 ps b,16 control and address input pulse width for each input tipw 620 - 560 - ps 28 calibration timing power - up and reset calibration time tzqinit m ax (512 nck, 640ns) - m ax (512 nck, 640ns) - normal operation full calibration time tzqoper m ax ( 256 nck, 320 ns) - m ax ( 256 nck, 320 ns) - normal operation short calibration time tzqcs m ax ( 64 nck, 8 0ns) - m ax ( 64 nck, 8 0ns) - 23 reset timing exit reset from cke high to a valid command txpr txprmin.: max(5nck, trfc(min) + 10ns) txprmax.: - self refresh timings exit self refresh to commands not requiring a locked dll txs txsmin.: max(5nck, trfc(min) + 10ns) txsmax.: -
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 66 rev. c 1 11/12 /2014 parameter symbol ddr3/ddr3l - 1333 ddr3/ddr3l - 1 600 units notes min. max. min. max. exit self refresh to commands requiring a locked dll txsdll txsdllmin.: tdllk(min) nck 2 txsdllmax.: - minimum cke low width for self refresh entry to exit timing tckesr tckesrmin.: tcke(min) + 1 nck tckesrmax.: - valid clock requirement after self refresh entry (sre) or power - down entry (pde) tcksre tcksremin.: max(5 nck, 10 ns) tcksremax.: - valid clock requirement before self refresh exit (srx) or power - down exit (pdx) or reset exit tcksrx tcksrxmin.: max(5 nck, 10 ns) tcksrxmax.: - power down timings exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll txp txpmin.: max(3nck, 6ns) txpmax.: - exit precharge power down with dll frozen to commands requiring a locked dll txpdll txpdllmin.: max(10nck, 24ns) txpdllmax.: - cke minimum pulse width tcke tckemin.: max(3nck 5.625ns) tckemin.: max(3nck 5ns) tckemax.: - tckemax.: - command pass disable delay tcpded tcpdedmin.: 1 nck tcpdedmax.: - power down entry to exit timing tpd tpdmin.: tcke(min) 15 tpdmax.: 9*trefi timing of act command to power down entry tactpden tactpdenmin.: 1 nck 20 tactpdenmax.: - timing of pre or prea command to power down entry tprpden tprpdenmin.: 1 nck 20 tprpdenmax.: - timing of rd/rda command to power down entry trdpden trdpdenmin.: rl+4+1 nck trdpdenmax.: - timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) twrpden twrpdenmin.: wl + 4 + (twr / tck(avg)) nck 9 twrpdenmax.: - timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) twrapden twrapdenmin.: wl+4+wr+1 nck 10 twrapdenmax.: - timing of wr command to power down entry (bc4mrs) twrpden twrpdenmin.: wl + 2 + (twr / tck(avg)) twrpdenmax.: - nck 9 timing of wra command to power down entry (bc4mrs) twrapden twrapdenmin.: wl + 2 +wr + 1 nck 10 twrapdenmax.: - timing of ref command to power down entry trefpden trefpdenmin.: 1 nck 20,21 trefpdenmax.: - timing of mrs command to power down entry tmrspden tmrspdenmin.: tmod(min) tmrspdenmax.: - odt timings odt high time without write command or with write command and bc4 odth4 odth4min.: 4 nck odth4max.: - odt high time with write command and bl8 odth8 odth8min.: 6 nck odth8max.: - asynchronous rtt turn - on delay (power - down with dll frozen) taonpd 2 8.5 2 8.5 ns asynchronous rtt turn - off delay (power - down with dll frozen) taofpd 2 8.5 2 8.5 ns rtt turn - on taon - 250 250 - 225 225 ps 7,f rtt_nom and rtt_wr turn - off time from odtloff reference taof 0.3 0.7 0.3 0.7 tck(avg) 8,f rtt dynamic change skew tadc 0.3 0.7 0.3 0.7 tck(avg) f
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 67 rev. c 1 11/12 /2014 parameter symbol ddr3/ddr3l - 1333 ddr3/ddr3l - 1 600 units notes min. max. min. max. write leveling timings first dqs/dqs# rising edge after write leveling mode is programmed twlmrd 40 - 40 - nck 3 dqs/dqs# delay after write leveling mode is programmed twldqsen 25 - 25 - nck 3 write leveling setup time from rising ck, ck# crossing to rising dqs, dqs# crossing twls 195 - 165 - ps write leveling hold time from rising dqs, dqs# crossing to rising ck, ck# crossing twlh 195 - 165 - ps write leveling output delay twlo 0 9 0 7.5 ns write leveling output error twloe 0 2 0 2 ns 9.3 timing parameter by speed bin (ddr3 - 1866 , ddr3 - 2133 ) parameter symbol ddr3/ddr3l - 1866 ddr3 - 2133 units notes min. max. min. max. clock timing minimum clock cycle time (dll off mode) tck(dll_off) 8 - 8 - ns 6 average clock period tck(avg) refer to standard speed bins ps average high pulse width tch(avg) 0.47 0.53 0.47 0.53 tck(avg) average low pulse width tcl(avg) 0.47 0.53 0.47 0.53 tck(avg) absolute clock period tck(abs) min.: tck(avg)min + tjit(per)min ps max.: tck(avg)max + tjit(per)max absolute clock high pulse width tch(abs) 0.43 - 0.43 - tck(avg) 25 absolute clock low pulse width tcl(abs) 0.43 - 0.43 - tck(avg) 26 clock period jitter jit(per) - 60 60 - 50 50 ps clock period jitter during dll locking period jit(per, lck) - 50 50 - 40 40 ps cycle to cycle period jitter tjit(cc) 120 120 100 100 ps cycle to cycle period jitter during dll locking period jit(cc, lck) 100 100 80 80 ps duty cycle jitter tjit(duty) - - - - ps cumulative error across 2 cycles terr(2per) - 88 88 - 74 74 ps cumulative error across 3 cycles terr(3per) - 105 105 - 87 87 ps cumulative error across 4 cycles terr(4per) - 117 117 - 97 97 ps cumulative error across 5 cycles terr(5per) - 126 126 - 105 105 ps cumulative error across 6 cycles terr(6per) - 133 133 - 111 111 ps cumulative error across 7 cycles terr(7per) - 139 139 - 116 116 ps cumulative error across 8 cycles terr(8per) - 145 145 - 121 121 ps cumulative error across 9 cycles terr(9per) - 150 150 - 125 125 ps cumulative error across 10 cycles terr(10per) - 154 154 - 128 128 ps cumulative error across 11 cycles terr(11per) - 158 158 - 132 132 ps cumulative error across 12 cycles terr(12per) - 161 161 - 134 134 ps cumulative error across n = 13, 14 . . . 49, 50 cycles terr(nper) terr(nper)min = (1 + 0.68ln(n)) * tjit(per)min ps terr(nper)max = (1 + 0.68ln(n)) * tjit(per)max data timing dqs, dqs# to dq skew, per group, per access tdqsq - 85 - 75 ps 13 dq output hold time from dqs, dqs# tqh 0.38 - 0.38 - tck(avg) 13,g dq low - impedance time from ck, ck# tlz(dq) - 390 195 - 360 180 ps 13,14,f dq high impedance time from ck, ck# thz(dq) - 195 - 180 ps 13,14,f data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels tds(base) ac135 see table for data setup and hold ps d,17 data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels tds(base) ac130 ps d,17
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 68 rev. c 1 11/12 /2014 parameter symbol ddr3/ddr3l - 1866 ddr3/ddr3l - 2133 units notes min. max. min. max. data hold time from dqs, dqs# referenced to vih(dc) / vil(dc) levels tdh(base) dc100 or dc90 see table for data setup and hold ps d,17 dq and dm input pulse width for each input tdipw 320 - 280 - ps 28 data strobe timing dqs,dqs# differential read preamble trpre 0.9 note 19 0.9 note 19 tck(avg) 13,19,g dqs, dqs# differential read postamble trpst 0.3 note 11 0.3 note 11 tck(avg) 11,13,g dqs, dqs# differential output high time tqsh 0.4 - 0.4 - tck(avg) 13,g dqs, dqs# differential output low time tqsl 0.4 - 0.4 - tck(avg) 13,g dqs, dqs# differential write preamble twpre 0.9 - 0.9 - tck(avg) 1 dqs, dqs# differential write postamble twpst 0.3 - 0.3 - tck(avg) 1 dqs, dqs# rising edge output access time from rising ck, ck# tdqsck - 195 195 - 180 180 ps 13,f dqs and dqs# low - impedance time (referenced from rl - 1) tlz(dqs) - 390 195 - 360 180 ps 13,14,f dqs and dqs# high - impedance time (referenced from rl + bl/2) thz(dqs) - 195 - 180 ps 13,14,f dqs, dqs# differential input low pulse width tdqsl 0.45 0.55 0.45 0.55 tck(avg) 29,31 dqs, dqs# differential input high pulse width tdqsh 0.45 0.55 0.45 0.55 tck(avg) 30,31 dqs, dqs# rising edge to ck, ck# rising edge tdqss - 0.27 0.27 - 0.27 0.27 tck(avg) c dqs, dqs# falling edge setup time to ck, ck# rising edge tdss 0.18 - 0.18 - tck(avg) c,32 dqs, dqs# falling edge hold time from ck, ck# rising edge tdsh 0.18 - 0.18 - tck(avg) c,32 command and address timing dll locking time tdllk 512 - 512 - nck internal read command to precharge command delay trtp trtpmin.: max(4nck, 7.5ns) trtpmax.: - delay from start of internal write transaction to internal read command twtr twtrmin.: max(4nck, 7.5ns) twtrmax.: write recovery time twr 15 - 15 - ns e,18 mode register set command cycle time tmrd 4 - 4 - nck mode register set command update delay tmod tmodmin.: max(12nck, 15ns) tmodmax.: act to internal read or write delay time trcd standard speed bins pre command period trp standard speed bins act to act or ref command period trc standard speed bins cas# to cas# command delay tccd 4 - 4 - nck auto precharge write recovery + precharge time tdal(min) wr + roundup(trp / tck(avg)) nck multi - purpose register recovery time tmprr 1 - 1 - nck 22 active to precharge command period tras standard speed bins active to active command period for 1kb page size trrd max(4nck, 6ns) - max(4nck, 6ns) - e active to active command period for 2kb page size trrd trrdmin.: max(4nck, 7.5ns) trrdmax.: four activate window for 1kb page size tfaw 27 - 25 - ns e four activate window for 2kb page size tfaw 35 - 35 - ns e command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) ac135 see table for add/c m d setup and hold ps b,16 command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis (base) ac125 ps b,16 command and address hold time from ck, ck# referenced to vih(dc) / vil(dc) levels tih(base) dc100 or dc90 ps b,16
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 69 rev. c 1 11/12 /2014 parameter symbol ddr3/ddr3l - 1866 ddr3/ddr3l - 2133 units notes min. max. min. max. control and address input pulse width for each input tipw 535 - 470 - ps 28 calibration timing power - up and reset calibration time tzqinit m ax (512 nck, 640ns) - m ax (512 nck, 640ns) - normal operation full calibration time tzqoper m ax ( 256 nck, 320 ns) - m ax ( 256 nck, 320 ns) - normal operation short calibration time tzqcs m ax ( 64 nck, 8 0ns) - m ax ( 64 nck, 8 0ns) - 23 reset timing exit reset from cke high to a valid command txpr txprmin.: max(5nck, trfc(min) + 10ns) txprmax.: - self refresh timings exit self refresh to commands not requiring a locked dll txs txsmin.: max(5nck, trfc(min) + 10ns) txsmax.: - exit self refresh to commands requiring a locked dll txsdll txsdllmin.: tdllk(min) nck txsdllmax.: - minimum cke low width for self refresh entry to exit timing tckesr tckesrmin.: tcke(min) + 1 nck tckesrmax.: - valid clock requirement after self refresh entry (sre) or power - down entry (pde) tcksre tcksremin.: max(5 nck, 10 ns) tcksremax.: - valid clock requirement before self refresh exit (srx) or power - down exit (pdx) or reset exit tcksrx tcksrxmin.: max(5 nck, 10 ns) tcksrxmax.: - power down timings exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll txp txpmin.: max(3nck, 6ns) txpmax.: - exit precharge power down with dll frozen to commands requiring a locked dll txpdll txpdllmin.: max(10nck, 24ns) 2 txpdllmax.: - cke minimum pulse width tcke tckemin.: max(3nck 5 ns) tckemax.: - command pass disable delay tcpded tcpdedmin.: 1 nck tcpdedmax.: - power down entry to exit timing tpd tpdmin.: tcke(min) 15 tpdmax.: 9*trefi timing of act command to power down entry tactpden 1 - 2 - nck 20 timing of pre or prea command to power down entry tprpden 1 - 2 - nck 20 timing of rd/rda command to power down entry trdpden trdpdenmin.: rl+4+1 nck trdpdenmax.: - timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) twrpden twrpdenmin.: wl + 4 + (twr / tck(avg)) nck 9 twrpdenmax.: - timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) twrapden twrapdenmin.: wl+4+wr+1 nck 10 twrapdenmax.: - timing of wr command to power down entry (bc4mrs) twrpden twrpdenmin.: wl + 2 + (twr / tck(avg)) twrpdenmax.: - nck 9 timing of wra command to power down entry (bc4mrs) twrapden twrapdenmin.: wl + 2 +wr + 1 nck 10 twrapdenmax.: - timing of ref command to power down entry trefpden 1 - 2 - nck 20,21 timing of mrs command to power down entry tmrspden tmrspdenmin.: tmod(min) tmrspdenmax.: - odt timings odt high time without write command or with write command and bc4 odth4 odth4min.: 4 nck odth4max.: -
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 70 rev. c 1 11/12 /2014 parameter symbol ddr3/ddr3l - 1866 ddr3/ddr3l - 2133 units notes min. max. min. max. odt high time with write command and bl8 odth8 odth8min.: 6 nck odth8max.: - asynchronous rtt turn - on delay (power - down with dll frozen) taonpd 2 8.5 2 8.5 ns asynchronous rtt turn - off delay (power - down with dll frozen) taofpd 2 8.5 2 8.5 ns rtt turn - on taon - 195 195 - 180 180 ps 7,f rtt_nom and rtt_wr turn - off time from odtloff reference taof 0.3 0.7 0.3 0.7 tck(avg) 8 ,f rtt dynamic change skew tadc 0.3 0.7 0.3 0.7 tck(avg) f write leveling timings first dqs/dqs# rising edge after write leveling mode is programmed twlmrd 40 - 40 - nck 3 dqs/dqs# delay after write leveling mode is programmed twldqsen 25 - 25 - nck 3 write leveling setup time from rising ck, ck# crossing to rising dqs, dqs# crossing twls 140 - 125 - ps write leveling hold time from rising dqs, dqs# crossing to rising ck, ck# crossing twlh 140 - 125 - ps write leveling output delay twlo 0 7.5 0 7.5 ns write leveling output error twloe 0 2 0 2 ns 9.4 timing notes 9.4.1 jitter specific note a unit tck(avg) represents the actual tck(avg) of the input clock under operation. unit nck represents one clock cycle of the input clock, counting the actual clock edges. ex) tmrd=4 [nck] means; if one mode register set command is registered at tm, another mode register set command may be registered at tm+4, even if (tm+4 - tm) is 4 x tck(avg) + terr(4per), min. specific note b these parameters are measured from a command/address signal (cke, cs, ras, cas, we, odt, ba0, a0, a1, etc) transition edge to its respective clock signal (ck/ck) crossing. the spec values are not affected by the amount of clock jitter appli ed (i.e. tjit(per), tjit(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. that is, these parameters should be met whether clock jitter is present or not. specific note c these parameters are mea sured from a data strobe signal (dqs(l/u), dqs(l/u)) crossing to its respective clock signal (ck, ck) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc), as these are relative to the clock signa l crossing. that is, these parameters should be met whether clock jitter is present or not. specific note d these parameters are measured from a data signal (dm(l/u), dq(l/u)0, dq(l/u)1, etc.) transition edge to its respective data strobe signal (dqs(l/u) , dqs(l/u)) crossing. specific note e for these parameters, the ddr3 sdram device supports tnparam [nck] = ru{tparam[ns] / tck(avg)[ns]}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. for example, the device will support tnrp =ru{trp/tck(avg)}, which is in clock cycles, if all input clock jitter specifications are met. this means: for ddr3 - 800 6 - 6 - 6, of which trp = 15ns, the device will support tnrp = ru{trp/tck(avg)} = 6, as long as the input clock jitter specific ations
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 71 rev. c 1 11/12 /2014 are met, i.e. precharge command at tm and active command at tm+6 is valid even if (tm+6 - tm) is less than 15ns due to input clock jitter. specific note f when the device is operated with input clock jitter, this parameter needs to be derated by the actual terr(mper), act of the input clock, where 2 <= m <=12. (output derating are relative to the sdram input clock.) for example, if the measured jitter into a ddr3 - 800 sdram has terr(mper),act,min = - 172ps and terr(mper),act,max = 193ps, then tdqsck,min (derated) = tdqsck,min - terr(mper),act,max = - 400ps - 193ps = - 593ps and tdqsck,max(derated) = tdqsck,max - err(mper),act,min = 400ps + 172ps = 572ps. similarly, tlz(dq) for ddr3 - 800 derates to tlz(dq),min(derated) = - 800ps - 193ps = - 993ps and tlz(dq),m ax(derated) = 400ps + 172ps = 572ps. (caution on the min/max usage!) note that terr(mper),act,min is the minimum measured value of terr(nper) where 2 <= n <= 12, and terr(mper),act,max is the maximum measured value of terr(nper) where 2 <= n <= 12. speci fic note g when the device is operated with input clock jitter, this parameter needs to be derated by the actual tjit(per),act of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr3 - 800 sdram has tck(avg),act=2500ps, tjit(per),act,min = - 72ps and tjit(per),act,max = 93ps, then trpre,min(derated) = trpre,min + tjit(per),act,min = 0.9 x tc k(avg),act + tjit(per),act,min = 0.9 x 2500ps - 72ps = 2178ps. similarly, tqh,min(derated) = tqh,min + tjit(per),act,min = 0.38 x tck(avg),act + tjit(per),act,min = 0.38 x 2500ps - 72ps = 878ps. (caution on the min/max usage!) 9.4.2 timing parameter s 1. actua l value dependent upon measurement level definitions. 2. commands requiring a locked dll are: read ( and rap) are synchronous odt commands. 3. the max values are system dependent. 4. wr as programmed in mode register. 5. value must be rouned - up to next higher integer value. 6. there is no maximum cycle time limit besides the need to satisfy the refresh interval, trefi. 7. for definition of rtt - on time taon see timing parameters. 8. for definition of rtt - off time taof see timing parameters. 9. twr is defined in ns, for calculat ion of twrpden it is necessary to round up twr / tck to the next integer. 10. wr in clock cycles are programmed in mr0. 11. the maximum read postamble is bonded by tdqsck(min) plus tqsh(min) on the left side and thz(dqs)max on the right side. 12. output timing deratin gs are relative to the sdram input clock. when the device is operated with input clock jitter, this parameter needs to be derated by tbd. 13. value is only valid for ron34. 14. single ended signal parameter. 15. trefi depends on toper. 16. tis(base) and tih(base) values a re for 1v/ns cmd/add single - ended slew rate and 2v/ns ck, ck differential slew rate. note for dq and dm signals, vref(dc)=vrefdq(dc). for input only pins except reset, vref(dc)=vrefca(dc). 17. tds(base) and tdh(base) values are for 1v/ns dq single - ended slew r ate and 2v/ns dqs, dqs differential slew rate. 18. note for dq and dm signals, vref(dc)=vrefdq(dc). for input only pins except reset, vref(dc)=vrefca(dc). 19. start of internal write transaction is defined as follows: 20. for bl8 (fixed by mrs and on - the - fly): rising clock edge 4 clock cycles after wl. 21. for bc4 (on - the - fly): rising clock edge 4 clock cycles after wl. 22. for bc4 (fixed by mrs): rising clock edge 2 clock cycles after wl. 19. the maximum preamble is bound by tlz(dqs)max on the left side and tdqsck(max) on the rig ht side. 20. cke is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power - down idd spec will not be applied until finishing those operations.
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 72 rev. c 1 11/12 /2014 21. although cke is allowed to be registered low after a refresh command once trefpden(min) is satisfied, there are cases where additional time such as txpdll(min) is also required. 22. defined between end of mpr read burst and mrs which reloads mpr or disables mp r function. 23. one zqcs command can effectively correct a minimum of 0.5% (zqcorrection) of ron and rtt impedance error within 64 nck for all speed bins assuming the maximum sensitivities specified in the output driver voltage and temperature sensitivity an d odt voltage and temperature sensitivity tables. the appropriate interval between zqcs commands can be determined from these tables and other application - specific parameters. 23. one method for calculating the interval between zqcs commands, given the tempe rature (tdriftrate) and voltage (vdriftrate) drift rates that the sdram is subject to in the application, is illustrated. the interval could be defined by th e following formula: zqcorrection / [(tsens x tdriftrate) + (vsens x vdriftrate)] , where tsens = max(drttdt, drondtm) and vsens = max(drttdv, drondvm) define the sdram temperature and voltage sensitivities. for example, if tsens = 1.5%/c, vsens = 0.15%/mv, tdriftrate = 1 c/sec and vdriftrate = 15mv/sec, then the interval between zqcs commands is calculated as 0.5 / [(1.5x1)+(0.15x15)] = 0.133 ? 24. n = from 13 cycles to 50 cycles. this row defines 38 parameters. 25. tch(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge. 26. tcl(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge. 27. the tis(base) ac150 specifications are adjusted from the tis(base) specification by adding an additional 100ps of derating t o accommodate for the lower altemate threshold of 150mv and another 25ps to account for the earlier reference point [(175mv - 150mv) / 1v/ns]. 28. pulse width of a input signal is defined as the width between the first crossing of vref(dc) and the consecutive crossing of vref(dc). 29. tdqsl describes the instantaneous differential input low pulse width on dqs - dqs#, as measured from one falling edge to the next consecutive rising edge. 30. tdqsh describes the instantaneous differential input high pulse width on dqs - dqs#, as measured from one rising edge to the next consecutive falling edge. 31. tdqsh,act + tdqsl,act = 1 tck,act ; with txyz,act being the actual measured value of the respective timing parameter in the application. 32. tdsh,act + tdss,act = 1 tck,act ; with txy z,act being the actual measured value of the respective timing parameter in the application.
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 73 rev. c 1 11/12 /2014 9.5 address / command setup, hold and derating for all input signals the total tis (setup time) and tih (hold time) required is calculated by adding the datasheet tis(base) and tih(base) value to the ? tis and ? tih derating value , respectively. example: tis (total setup time) = tis(base) + ? tis setup ( tis) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vih(ac)min. setup (tis) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of vil(ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded vref(dc) to ac region, use nominal slew rate for derating value . if the actual signal is later than the nominal slew rate line anywhere between shaded vref(dc) to ac region, the slew rate of a tangent line to the actual signal from the ac level to vref (dc) level is used for derating value. hold (tih) nominal slew rate for a rising signal is defined as the slew rate betwe en the last crossing of vil(dc)max and the first crossing of vref(dc). hold (tih) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc)min and the first crossing of vref(dc). if the actual signal is always later than the nominal slew rate line between shaded dc to vref(dc) region, use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded dc to vref(dc) region, the slew rate of a tang ent line to the actual signal from the dc level to vref (dc) level is used for derating value. for a valid transition the input signal has to remain above/below vih/il(ac) for some time tvac. although for slow slew rates the total setup time might be nega tive (i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock transition, a valid input signal is still required to complete the transition and reach vih/il(ac). for slew rat es in between the values listed in the t able s , the derating values may obtained by linear interpolation. these values are typically not subject to production test. they are verified by design and characterization. 9.5.1 add/cmd setup and hold base - values for 1v/ns ddr3/ ddr3l symbol reference ddr3 - 800 ddr3 - 1066 ddr3 - 1333 ddr3 - 1600 ddr3 - 1866 ddr3 - 2133 units ddr3 tis(base) ac175 vih/l(ac) 200 125 65 45 - - ps tis(base) ac150 vih/l(ac) 350 275 190 170 - - ps tis(base) ac135 vih/l(ac) - - - - 65 60 ps tis(base) ac125 vih/l(ac) - - - - 150 135 ps tih(base) dc100 vih/l(dc) 275 200 140 120 100 95 ps ddr3l tis(base) ac160 vih/l(ac) 215 140 80 60 - - ps tis(base) ac135 vih/l(ac) 365 290 205 185 65 - ps tis(base) ac125 vih/l(ac) - - - - 150 - ps tih(base) dc90 vih/l(dc) 285 210 150 130 110 - ps note: (ac/dc referenced for 1v/ns address/command slew rate and 2 v/ns differential ck - ck# slew rate)
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 74 rev. c 1 11/12 /2014 9.5.2 derating values [ps] for ddr3l - 800/1066/1333/1600 tis/tih - ac/dc based ac160 threshold ac160 threshold - > vih(ac) = vref(dc) + 160mv, vil(ac) = vref(dc) - 160mv ddr3l ck, ck# differential slew rate 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd/add slew rate v/ns 2 80 45 80 45 80 45 88 53 96 61 104 69 112 79 120 95 1.5 53 30 53 30 53 30 61 38 69 46 77 54 85 64 93 80 1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 - 1 - 3 - 1 - 3 - 1 - 3 7 5 15 13 23 21 31 31 39 47 0.8 - 3 - 8 - 3 - 8 - 3 - 8 5 1 13 9 21 17 29 27 37 43 0.7 - 5 - 13 - 5 - 13 - 5 - 13 3 - 5 11 3 19 11 27 21 35 37 0.6 - 8 - 20 - 8 - 20 - 8 - 20 0 - 12 8 - 4 16 4 24 14 32 30 0.5 - 20 - 30 - 20 - 30 - 20 - 30 - 12 - 22 - 4 - 14 4 - 6 12 4 20 20 0.4 - 40 - 45 - 40 - 45 - 40 - 45 - 32 - 37 - 24 - 29 - 16 - 21 - 8 - 11 0 5 9.5.3 derating values [ps] for ddr3l - 800/1066/1333/1600 tis/tih - ac/dc based ac135 threshold ac135 threshold - > vih(ac) = vref(dc) + 135mv, vil(ac) = vref(dc) - 135mv ddr3l ck, ck# differential slew rate 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd/add slew rate v/ns 2 68 45 68 45 68 45 76 53 84 61 92 69 100 79 108 95 1.5 45 30 45 30 45 30 53 38 61 46 69 54 77 64 85 80 1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 2 - 3 2 - 3 2 - 3 10 5 18 13 26 21 34 31 42 47 0.8 3 - 8 3 - 8 3 - 8 11 1 19 9 27 17 35 27 43 43 0.7 6 - 13 6 - 13 6 - 13 14 - 5 22 3 30 11 38 21 46 37 0.6 9 - 20 9 - 20 9 - 20 17 - 12 25 - 4 33 4 41 14 49 30 0.5 5 - 30 5 - 30 5 - 30 13 - 22 21 - 14 29 - 6 37 4 45 20 0.4 - 3 - 45 - 3 - 45 - 3 - 45 6 - 37 14 - 29 22 - 21 30 - 11 38 5 9.5.4 derating values [ps] for ddr3l - 1866 tis/tih - ac/dc based ac125 threshold ac125 threshold - > vih(ac) = vref(dc) + 125mv, vil(ac) = vref(dc) - 125mv ddr3l ck, ck# differential slew rate 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd/add slew rate v/ns 2 63 45 63 45 63 45 71 53 79 61 87 69 95 79 103 95 1.5 42 30 42 30 42 30 50 38 58 46 66 54 74 64 82 80 1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 3 - 3 3 - 3 3 - 3 11 5 19 13 27 21 35 31 43 47 0.8 6 - 8 6 - 8 6 - 8 14 1 22 9 30 17 38 27 46 43 0.7 10 - 13 10 - 13 10 - 13 18 - 5 26 3 34 11 42 21 50 37 0.6 16 - 20 16 - 20 16 - 20 24 - 12 32 - 4 40 4 48 14 56 30 0.5 15 - 30 15 - 30 15 - 30 23 - 22 31 - 14 39 - 6 47 4 55 20 0.4 13 - 45 13 - 45 13 - 45 21 - 37 29 - 29 37 - 21 45 - 11 53 5
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 75 rev. c 1 11/12 /2014 9.5.5 derating values [ps] for ddr3 - 800/1066/1333/1600 tis/tih - ac/dc based ac175 threshold ac175 threshold - > vih(ac) = vref(dc ) + 175mv, vil(ac) = vref(dc) - 175mv ddr3 ck, ck# differential slew rate 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd/add slew rate v/ns 2 88 50 88 50 88 50 96 58 104 66 112 74 120 84 128 100 1.5 59 34 59 34 59 34 67 42 75 50 83 58 91 68 99 84 1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 - 2 - 4 - 2 - 4 - 2 - 4 6 4 14 12 22 20 30 30 38 46 0.8 - 6 - 10 - 6 - 10 - 6 - 10 2 - 2 10 6 18 14 26 24 34 40 0.7 - 11 - 16 - 11 - 16 - 11 - 16 - 3 - 8 5 0 13 8 21 18 29 34 0.6 - 17 - 26 - 17 - 26 - 17 - 26 - 9 - 18 - 1 - 10 7 - 2 15 8 23 24 0.5 - 35 - 40 - 35 - 40 - 35 - 40 - 27 - 32 - 19 - 24 - 11 - 16 - 2 - 6 5 10 0.4 - 62 - 60 - 62 - 60 - 62 - 60 - 54 - 52 - 46 - 44 - 38 - 36 - 30 - 26 - 22 - 10 9.5.6 derating values [ps] for ddr3 - 800/1066/1333/1600 tis/tih - ac/dc based ac150 threshold ac150 threshold - > vih(ac) = vref(dc) + 150mv, vi l(ac) = vref(dc) - 150mv ddr3 ck, ck# differential slew rate 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd/add slew rate v/ns 2 75 50 75 50 75 50 83 58 91 66 99 74 107 84 115 100 1.5 50 34 50 34 50 34 58 42 66 50 74 58 82 68 90 84 1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 0 - 4 0 - 4 0 - 4 8 4 16 12 24 20 32 30 40 46 0.8 0 - 10 0 - 10 0 - 10 8 - 2 16 6 24 14 32 24 40 40 0.7 0 - 16 0 - 16 0 - 16 8 - 8 16 0 24 8 32 18 40 34 0.6 - 1 - 26 - 1 - 26 - 1 - 26 7 - 18 15 - 10 23 - 2 31 8 39 24 0.5 - 10 - 40 - 10 - 40 - 10 - 40 - 2 - 32 6 - 24 14 - 16 22 - 6 30 10 0.4 - 25 - 60 - 25 - 60 - 25 - 60 - 17 - 52 - 9 - 44 - 1 - 36 7 - 26 15 - 10 9.5.7 derating values [ps] for ddr3 - 1866/2133 tis/tih - ac/dc based ac135 threshold ac135 threshold - > vih(ac) = vref(dc) + 135mv, vil(ac) = vref(dc) - 135mv ddr3 ck, ck# differential slew rate 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd/add slew rate v/ns 2 68 50 68 50 68 50 76 58 84 66 92 74 100 84 108 100 1.5 45 34 45 34 45 34 53 42 61 50 69 58 77 68 85 84 1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 2 - 4 2 - 4 2 - 4 10 4 18 12 26 20 34 30 42 46 0.8 3 - 10 3 - 10 3 - 10 11 - 2 19 6 27 14 35 24 43 40 0.7 6 - 16 6 - 16 6 - 16 14 - 8 22 0 30 8 38 18 46 34 0.6 9 - 26 9 - 26 9 - 26 17 - 18 25 - 10 33 - 2 41 8 49 24 0.5 5 - 40 5 - 40 5 - 40 13 - 32 21 - 24 29 - 16 37 - 6 45 10 0.4 - 3 - 60 - 3 - 60 - 3 - 60 6 - 52 14 - 44 22 - 36 30 - 26 38 - 10
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 76 rev. c 1 11/12 /2014 9.5.8 derating values [ps] for ddr3 - 1866/2133 tis/tih - ac/dc based ac125 threshold ac125 threshold - > vih(ac) = vref(dc) + 125mv, vil(ac) = vref(dc) - 125mv ddr3 ck, ck# differential slew rate 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd/add slew rate v/ns 2 63 50 63 50 63 50 71 58 79 66 87 74 95 84 103 100 1.5 42 34 42 34 42 34 50 42 58 50 66 58 74 68 82 84 1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 4 - 4 4 - 4 4 - 4 12 4 20 12 28 20 36 30 44 46 0.8 6 - 10 6 - 10 6 - 10 14 - 2 22 6 30 14 38 24 46 40 0.7 11 - 16 11 - 16 11 - 16 19 - 8 27 0 35 8 43 18 51 34 0.6 16 - 26 16 - 26 16 - 26 24 - 18 32 - 10 40 - 2 48 8 56 24 0.5 15 - 40 15 - 40 15 - 40 23 - 32 31 - 24 39 - 16 47 - 6 55 10 0.4 13 - 60 13 - 60 13 - 60 21 - 52 29 - 44 37 - 36 45 - 26 53 - 10 9.5.9 required minimum time tvac above vih(ac) {below vil(ac)} for valid add/cmd transition slew rate [v/ns] ddr3 ddr3l 800/1066/1333/1600 1866/2133 800/1066/1333/1600 1866 175mv [ps] 150mv [ps] 135mv [ps] 125mv [ps] 160mv [ps] 135mv [ps] 135mv [ps] 125mv [ps] > 2.0 75 175 168 173 200 213 200 205 2 57 170 168 173 200 213 200 205 1.5 50 167 145 152 173 190 178 184 1 38 130 100 110 120 145 133 143 0.9 34 113 85 96 102 130 118 129 0.8 29 93 66 79 80 111 99 111 0.7 22 66 42 56 51 87 75 89 0.6 note 30 10 27 13 55 43 59 0.5 note note note note note 10 note 18 < 0.5 note note note note note 10 note 18 note: the rising input signal shall become equal to or greater than vih(ac) level; and the falling input signal shall become equal to or less than vil(ac) level.
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 77 rev. c 1 11/12 /2014 9.5.10 address / command setup, hold and derating 9. 5 .10 .1 nominal slew rate and tvac for setup time tis(left) and hold time t i h(right) C add/cmd with respect to clock 9.5 .10 .2 tangent line for setup time tis(left) and hold time tih(right) - add/cmd with respect to clock ck # ck # v ref to ac region ck v ddq vih(ac)min vih(dc)min vref(dc) vi l(d c)max vi l ( ac)max no minal slew rate no minal slew rate tis tih tvac tvac tis tih v ss ? tf ? t r setup slew rate @ falling signal = [vref( dc) - vil(ac)max] / tf setup slew rate @ rising signal = [vih(ac)min - vref(dc)] / t r ck v ddq vih(ac)min vih(dc)min vref(dc) vi l(d c)max vi l ( ac)max no minal slew rate no minal slew rate tis tih tvac tis tih v ss ? t r ? t f hold slew rate @ rising signal = [vref(dc) - vil(dc)max] / t r hold slew rate @ falling signal = [vih(dc)min - vref(dc)] / t f ck # ck v ddq vih(ac)min vih(dc)min vref(dc) vi l(d c)max vi l ( ac)max no minal slew rate no minal slew rate tis tih tvac tvac tis tih v ss ? tf ? t r setup slew rate @ rising signal = tangent line [vih(ac)min - vref(dc)] / t r setup slew rate @ falling signal = tangent line [vref(dc) - vil(ac)max] / t f tangent line tangent line ck # ck v ddq vih( ac)min vih(dc)min vref(dc) vi l(d c)max vi l ( ac)max no minal slew rate no minal slew rate tis tih tis tih v ss ? t r hold slew rate @ falling signal = tangent line [vih(dc)min - vref(dc)] / t f hold slew rate @ rising signal = tangent line [vref(dc) - vil(dc)max] / t r tangent line tangent line ? t f v ref to ac region v ref to d c region v ref to d c region
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 78 rev. c 1 11/12 /2014 9 .6 data setup, hold and slew rate derating for all input signals the total tds (setup time) and tdh (hold time) required is calculated by adding the data sheet t ds(base) and tdh(bas e) value (see corresponding t able s ) to the ? tds and ? tdh (see corresponding tables ) derating value respectively. example: tds (t otal setup time) = tds(base) + ? tds. setup (tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of v ih(ac) min. setup (td s) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vil(ac) max. if the actual signal is always earlier than the nominal slew rate line between shaded vref(dc) to ac region , use nominal slew rate for derating value. if the actual signal is later than the nominal slew rate line anywhere between shaded vref(dc) to ac region, the slew rate of a tangent line to the actual signal from the ac level to vref(dc) level is used for derating value. hold (tdh) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc) max and the first crossing of vref(dc) . hold (tdh) nominal slew rate for a falling signal is defined as the slew rate betwee n the last crossing of vih(dc) min and the first crossing of vref(dc). if the actual signal is always later than the nominal slew rate line between shaded dc level to vref(dc) region, use nominal slew rate for derating value. if the actual signal is earl ier than the nominal slew rate line anywhere between shaded dc to v ref(dc) region, the slew rate of a tangent line to the actual signal from the dc level to vref(dc) le vel is used for derating value . for a valid transition the input signal has to remai n above/below vih/il(ac) for some time tvac . although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach vih/il(ac) . for slew rates in between the values listed in the tables , the derating values may obtained by linear interpolation. these values are typically not subject to production test. they are verified by design and characterization. 9.6.1 data setup and hold base - values symbol reference ddr3 - 800 ddr3 - 1066 ddr3 - 1333 ddr3 - 1600 ddr3 - 1866 ddr3 - 2133 units ddr3 tds(base) ac175 vih/l(ac), sr= 1v/ns 75 25 - - - - ps tds(base) ac150 vih/l(ac), sr= 1v/ns 125 75 30 10 - - ps tds(base) ac135 vih/l(ac), sr= 1v/ns 165 115 60 40 - - ps tds(base) ac135 vih/l(ac), sr= 2v/ns - - - - 68 53 ps tdh(base) dc100 vih/l(dc), sr= 1v/ns 150 100 65 45 - - ps tdh(base) dc100 vih/l(dc), sr= 2v/ns - - - - 70 55 ps ddr3l tds(base) ac160 vih/l(ac), sr= 1v/ns 90 40 - - - - ps tds(base) ac135 vih/l(ac), sr= 1v/ns 140 90 45 25 - - ps tds(base) ac130 vih/l(ac), sr= 2v/ns - - - - 70 - ps tdh(base) dc90 vih/l(dc), sr= 1v/ns 160 110 75 55 - - ps tdh(base) dc90 vih/l(dc), sr= 2v/ns - - - - 75 - ps note: ( note: ac/dc referenced for 2v/ns dq - slew rate and 4v/ns dqs slew rate, or 1v/ns dq - slew rate and 2v/ns dqs slew rate, as shown.
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 79 rev. c 1 11/12 /2014 9.6.2 derating values [ps] for ddr3l - 800/1066 tds/tdh - ac/dc based ac160 ac160 threshold - > vih(ac) = vref(dc) + 160mv, vil(ac) = vref(dc) - 160mv ddr3l dqs, dqs# differential slew rate 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh dq slew rate v/ns 2 80 45 80 45 80 45 - - - - - - - - - - 1.5 53 30 53 30 53 30 61 38 - - - - - - - - 1 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - - 1 - 3 - 1 - 3 7 5 15 13 23 21 - - - - 0.8 - - - - - 3 - 8 5 1 13 9 21 17 29 27 - - 0.7 - - - - - - 3 - 5 11 3 19 11 27 21 35 37 0.6 - - - - - - - - 8 - 4 16 4 24 14 32 30 0.5 - - - - - - - - - - 4 - 6 12 4 20 20 0.4 - - - - - - - - - - - - - 8 - 11 0 5 9.6.3 derating values [ps] for ddr3l - 800/1066/1333/1600 tds/tdh - ac/dc based ac135 threshold ac135 threshold - > vih(ac) = vref(dc) + 135mv, vil(ac) = vref(dc) - 135mv ddr3l dqs, dqs# differential slew rate 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh dq slew rate v/ns 2 68 45 68 45 68 45 - - - - - - - - - - 1.5 45 30 45 30 45 30 53 38 - - - - - - - - 1 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - 2 - 3 2 - 3 10 5 18 13 26 21 - - - - 0.8 - - - - 3 - 8 11 1 19 9 27 17 35 27 - - 0.7 - - - - - - 14 - 5 22 3 30 11 38 21 46 37 0.6 - - - - - - - - 25 - 4 33 4 41 14 49 30 0.5 - - - - - - - - - - 29 - 6 37 4 45 20 0.4 - - - - - - - - - - - - 30 - 11 38 5 9.6.4 derating values [ps] for ddr3l - 1866 tds/tdh - ac/dc based ac130 threshold ac130 threshold - > vih(ac) = vref(dc) + 130mv, vil(ac) = vref(dc) - 130mv ddr3l dqs, dqs# differential slew rate 8.0v/ns 7.0v/ns 6.0v/ns 5.0v/ns 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh dq slew rate v/ns 4 33 23 33 23 33 23 - - - - - - - - - - - - - - - - - - 3.5 28 19 28 19 28 19 28 19 - - - - - - - - - - - - - - - - 3 22 15 22 15 22 15 22 15 22 15 - - - - - - - - - - - - - - 2.5 - - 13 9 13 9 13 9 13 9 13 9 - - - - - - - - - - - - 2 - - - - 0 0 0 0 0 0 0 0 0 0 - - - - - - - - - - 1.5 - - - - - - - 22 - 15 - 22 - 15 - 22 - 15 - 22 - 15 - 14 - 7 - - - - - - - - 1 - - - - - - - - - 65 - 45 - 65 - 45 - 65 - 45 - 57 - 37 - 49 - 29 - - - - - - 0.9 - - - - - - - - - - - 62 - 48 - 62 - 48 - 54 - 40 - 46 - 32 - 38 - 24 - - - - 0.8 - - - - - - - - - - - - - 61 - 53 - 53 - 45 - 45 - 37 - 37 - 29 - 29 - 19 - - 0.7 - - - - - - - - - - - - - - - 49 - 50 - 41 - 42 - 33 - 34 - 25 - 24 - 17 - 8 0.6 - - - - - - - - - - - - - - - - - 37 - 49 - 29 - 41 - 21 - 31 - 13 - 15 0.5 - - - - - - - - - - - - - - - - - - - 31 - 51 - 23 - 41 - 15 - 25 0.4 - - - - - - - - - - - - - - - - - - - - - 28 - 56 - 20 - 40
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 80 rev. c 1 11/12 /2014 9.6.5 derating values [ps] for ddr3 - 800/1066 tds/tdh - ac/dc based ac175 threshold ac175 threshold - > vih(ac) = vref(dc) + 175mv, vil(ac) = vref(dc) - 175mv ddr3 dqs, dqs# differential slew rate 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh dq slew rate v/ns 2 88 50 88 50 88 50 - - - - - - - - - - 1.5 59 34 59 34 59 34 67 42 - - - - - - - - 1 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - - 2 - 4 - 2 - 4 6 4 14 12 22 20 - - - - 0.8 - - - - - 6 - 10 2 - 2 10 6 18 14 26 24 - - 0.7 - - - - - - - 3 - 8 5 0 13 8 21 18 29 34 0.6 - - - - - - - - - 1 - 10 7 - 2 15 8 23 24 0.5 - - - - - - - - - - - 11 - 16 - 2 - 6 5 10 0.4 - - - - - - - - - - - - - 30 - 26 - 22 - 10 9.6.6 derating values [ps] for ddr3 - 800/1066/1333/1600 tds/tdh - ac/dc based ac150 threshold ac150 threshold - > vih(ac) = vref(dc) + 150mv, vi l(ac) = vref(dc) - 150mv ddr3 dqs, dqs# differential slew rate 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh dq slew rate v/ns 2 75 50 75 50 75 50 - - - - - - - - - - 1.5 50 34 50 34 50 34 58 42 - - - - - - - - 1 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - 0 - 4 0 - 4 8 4 16 12 24 20 - - - - 0.8 - - - - 0 - 10 8 - 2 16 6 24 14 32 24 - - 0.7 - - - - - - 8 - 8 16 0 24 8 32 18 40 34 0.6 - - - - - - - - 15 - 10 23 - 2 31 8 39 24 0.5 - - - - - - - - - - 14 - 16 22 - 6 30 10 0.4 - - - - - - - - - - - - 7 - 26 15 - 10 9.6.7 derating values [ps] for ddr3 - 1866/2133 tds/tdh - ac/dc based ac135 threshold ac135 threshold - > vih(ac) = vref(dc) + 135mv, vil(ac) = v ref(dc) - 135mv dc100 threshold - > vih(dc) = vref(dc) + 100mv, vil(dc) = vref(dc) - 100mv ddr3 dqs, dqs# differential slew rate 8.0v/ns 7.0v/ns 6.0v/ns 5.0v/ns 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh dq slew rate v/ns 4 34 25 34 25 34 25 - - - - - - - - - - - - - - - - - - 3.5 29 21 29 21 29 21 29 21 - - - - - - - - - - - - - - - - 3 23 17 23 17 23 17 23 17 23 17 - - - - - - - - - - - - - - 2.5 - - 14 10 14 10 14 10 14 10 14 10 - - - - - - - - - - - - 2 - - - - 0 0 0 0 0 0 0 0 0 0 - - - - - - - - - - 1.5 - - - - - - - 23 - 17 - 23 - 17 - 23 - 17 - 23 - 17 - 15 - 9 - - - - - - - - 1 - - - - - - - - - 68 - 50 - 68 - 50 - 68 - 50 - 60 - 42 - 52 - 34 - - - - - - 0.9 - - - - - - - - - - - 66 - 54 - 66 - 54 - 58 - 46 - 50 - 38 - 42 - 30 - - - - 0.8 - - - - - - - - - - - - - 64 - 60 - 56 - 52 - 48 - 44 - 40 - 36 - 32 - 26 - - 0.7 - - - - - - - - - - - - - - - 53 - 59 - 45 - 51 - 37 - 43 - 29 - 33 - 21 - 17 0.6 - - - - - - - - - - - - - - - - - 43 - 61 - 35 - 53 - 27 - 43 - 19 - 27 0.5 - - - - - - - - - - - - - - - - - - - 39 - 66 - 31 - 56 - 23 - 40 0.4 - - - - - - - - - - - - - - - - - - - - - 36 - 76 - 30 - 60
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 81 rev. c 1 11/12 /2014 9.6.8 derating values [ps] for ddr3 - 800/1066/1333/1600 tds/tdh - ac/dc based ac135 threshold ac135 threshold - > vih(ac) = vref(dc) + 135mv, vil(ac) = vref(dc) - 135mv dc100 threshold - > vih(dc) = vref(dc) + 100mv, vil(dc) = vref(dc) - 100mv ddr3 dqs, dqs# differential slew rate 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh dq slew rate v/ns 2 68 50 68 50 68 50 - - - - - - - - - - 1.5 45 34 45 34 45 34 53 42 - - - - - - - - 1 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - 2 - 4 2 - 4 10 4 18 12 26 20 - - - - 0.8 - - - - 3 - 10 11 - 2 19 6 27 14 35 24 - - 0.7 - - - - - - 14 - 8 22 0 30 8 38 18 46 34 0.6 - - - - - - - - 25 - 10 33 - 2 41 8 49 24 0.5 - - - - - - - - - - 29 - 16 37 - 6 45 10 0.4 - - - - - - - - - - - - 30 - 26 38 - 10 9.6.9 required minimum time tvac [ps] above vih(ac) {below vil(ac)} for valid dq transition slew rate [v/ns] ddr3 ddr3l 800/1066 800/1066/1333/1600 800/1066/1333/1600 1866 2133 800/1066 800/1066/1333/1600 1866 ac175 ac150 ac135 ac160 ac135 ac130 > 2.0 75 105 113 93 73 165 113 95 2 57 105 113 93 73 165 113 95 1.5 50 80 90 70 50 138 90 73 1 38 30 45 25 5 85 45 30 0.9 34 13 30 note note 67 30 16 0.8 29 note 11 note note 45 11 note 0.7 note note note - - 16 note - 0.6 note note note - - note note - 0.5 note note note - 2 note note - < 0.5 note note note - - note note - note: the rising input signal shall become equal to or greater than vih(ac) level; and the falling input signal shall become equal to or less than vil(ac) level
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 82 rev. c 1 11/12 /2014 9.6.10 data setup, hold and slew rate derating 9.6. 10 .1 n ominal slew rate and tvac for setup time tds (left) and hold time t dh (right) - dq with respect to strobe 9.6.10 .2 tangent line for setup time tds(left) and hold time tdh(right) - dq with respect to strobe dqs v ddq vih(ac)min vih(dc)min vref(dc) vi l(d c)max vi l ( ac)max n ominal slew rate n ominal slew rate tds tdh tvac tvac tds tdh v ss ? tf ? t r setup slew rate @ falling signal = [vref(dc) - vil(ac)max] / tf setup slew rate @ rising signal = [vih(ac)min - vref(dc)] / t r dqs v ddq vih(ac)min vih(dc)min vref(dc) vi l(d c)max vi l ( ac)max no minal slew rate no minal slew rate tds tdh tvac tds tdh v ss ? t r ? t f hold slew rate @ rising signal = [vref(dc) - vil(dc)max] / t r hold slew rate @ falling signal = [vih(dc)min - vref(dc)] / t f dqs# dqs v ddq vih(ac)min vih(dc)min vref(dc) vi l(d c)max vi l ( ac)max no minal slew rate no minal slew rate tds tdh tvac tvac tds tdh v ss ? tf ? t r setup slew rate @ rising signal = tangent line [vih(ac)min - vref(dc)] / t r setup slew rate @ falling signal = tangent line [vref(dc) - vil(ac)max] / t f tangent line tangent line dqs# dqs v ddq vih(ac)min vih(dc)min vref(dc) vi l(d c)max vi l ( ac)max no minal slew rate no minal slew rate tds tdh tds tdh v ss ? t r hold slew rate @ falling signal = tangent line [vih(dc)min - vref(dc)] / t f hold slew rate @ rising signal = tangent line [vref(dc) - vil(dc)max] / t r tangent line tangent line ? t f v ref to ac region v ref to d c region v ref to ac region v ref to d c region
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 83 rev. c 1 11/12 /2014 ordering information , 64mx16, 1.5v (ddr3 ) 64mx16 - commercial range: (0c ? c ? data rate cl - trcd - trp order part no. package 1333 mt/s 8 - 8 - 8 is43tr16640 b - 15gbl 96 - ball fbga,lead - free 1600 mt/s 10 - 10 - 10 is43tr16640 b - 125jbl 96 - ball fbga,lead - free 1866mt/s 13 - 13 - 13 is43tr16640b - 107mbl 96 - ball fbga,lead - free 2133mt/s 14 - 14 - 14 is43tr16640b - 093nbl 96 - ball fbga,lead - free 64mx16 - industrial range: ( C 40c ? c ? data rate cl - trcd - trp order part no. package 1333 mt/s 8 - 8 - 8 is43tr16640 b - 15gbli 96 - ball fbga,lead - free 1600 mt/s 10 - 10 - 10 is43tr16640b - 125jbli 96 - ball fbga,lead - free 1866mt/s 13 - 13 - 13 is43tr16440b - 107mbli 96 - ball fbga, lead - free 2433mt/s 14 - 14 - 14 is43tr16440b - 093nbli 96 - ball fbga, lead - free 64mx16 C automotive, a1 range: ( C 40c ? c ? data rate cl - trcd - trp order part no. package 1333 mt/s 8 - 8 - 8 is46 tr16640 b - 15gbla1 96 - ball fbga,lead - free 1600 mt/s 10 - 10 - 10 is46tr16640 b - 125jbla1 96 - ball fbga,lead - free 64mx16 C automotive, a2 range: ( C 40c ? c ? data rate cl - trcd - trp order part no. package 1333 mt/s 8 - 8 - 8 is46 tr16640 b - 15gbla2 96 - ball fbga,lead - free 1600 mt/s 10 - 10 - 10 is46tr16640 b - 125jbla2 96 - ball fbga,lead - free note: contact issi for availability of options.
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 84 rev. c 1 11/12 /2014 o rdering information, 128mx8, 1. 5v (ddr3) 128mx8 - commercial range: (0c ? c ? data rate cl - trcd - trp order part no. package 1333 mt/s 8 - 8 - 8 is43tr81280b - 15gbl 78 - ball fbga,lead - free 1600 mt/s 10 - 10 - 10 is43tr81280b - 125jbl 78 - ball fbga,lead - free 1866mt/s 13 - 13 - 13 is43tr81280b - 107mbl 78 - ball fbga,lead - free 128mx8 - industrial range: ( C 40c ? c ? data rate cl - trcd - trp order part no. package 1333 mt/s 8 - 8 - 8 is43tr81280b - 15gbli 78 - ball fbga,lead - free 1600 mt/s 10 - 10 - 10 is43tr81280b - 125jbli 78 - ball fbga,lead - free 1866mt/s 13 - 13 - 13 is43tr81280b - 107mbli 78 - ball fbga,lead - free 128mx8 C automotive, a1 range: ( C 40c ? c ? data rate cl - trcd - trp order part no. package 1333 mt/s 8 - 8 - 8 is46tr81280b - 15gbla1 78 - ball fbga,lead - free 1600 mt/s 10 - 10 - 10 is46tr81280b - 125jbla1 78 - ball fbga,lead - free 128mx8 C automotive, a2 range: ( C 40c ? c ? data rate cl - trcd - trp order part no. package 1333 mt/s 8 - 8 - 8 is46tr81280b - 15gbla2 78 - ball fbga,lead - free 1600 mt/s 10 - 10 - 10 is46tr81280b - 125jbla2 78 - ball fbga,lead - free note: contact issi for availability of options.
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 85 rev. c 1 11/12 /2014 ordering information , 64mx16, 1.35v (ddr3l) 64mx16 - commercial range: (0c ? c ? data rate cl - trcd - trp order part no. package 1600 mt/s 10 - 10 - 10 is43tr16640 b l - 125jbl 96 - ball fbga,lead - free 1866 mt/s 13 - 13 - 13 IS43TR16640BL - 107mbl 96 - ball fbga,lead - free 64mx16 - industrial range: ( C 40c ? c ? data rate cl - trcd - trp order part no. package 1600 mt/s 10 - 10 - 10 is43tr16640 b l - 125jbli 96 - ball fbga,lead - free 1866 mt/s 13 - 13 - 13 IS43TR16640BL - 107mbli 96 - ball fbga,lead - free 64mx16 C automotive, a1 range: ( C 40c ? c ? data rate cl - trcd - trp order part no. package 1600 mt/s 10 - 10 - 10 is46tr16640 b l - 125jbla1 96 - ball fbga,lead - free 64mx16 C automotive, a2 range: ( C 40c ? c ? data rate cl - trcd - trp order part no. package 1600 mt/s 10 - 10 - 10 is46tr16640bl - 125jbla2 96 - ball fbga,lead - free note: contact issi for availability of options.
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 86 rev. c 1 11/12 /2014 o rdering information, 128mx8, 1.3 5v (ddr3l) 128mx8 - commercial range: (0c ? c ? data rate cl - trcd - trp order part no. package 1600 mt/s 10 - 10 - 10 is43tr81280 b l - 125jbl 78 - ball fbga,lead - free 1866mt/s 13 - 13 - 13 is43tr81280bl - 107mbl 78 - ball fbga,lead - free 128mx8 - industrial range: ( C 40c ? c ? data rate cl - trcd - trp order part no. package 1600 mt/s 10 - 10 - 10 is43tr81280 b l - 125jbli 78 - ball fbga,lead - free note: contact issi for availability of options.
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 87 rev. c 1 11/12 /2014
is4 3 /46 tr16640 b , is4 3 /46 tr16640 bl is43 /46tr81280b, is43 /46 tr81280 bl integrated silicon solution, inc. C www.issi.com C 88 rev. c 1 11/12 /2014

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